SNLA266B August   2016  – April 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I

 

  1.   1
  2.   DP8382x IEEE 802.3u Compliance and Debug
  3.   Trademarks
  4. 1Terminology
  5. 2Standards and System Requirements
    1. 2.1 Standards
    2. 2.2 Test Equipment Suppliers
    3. 2.3 Test Equipment Requirements
  6. 3Ethernet Physical Layer Compliance Testing
    1. 3.1 Standard Test Setup and Procedures
    2. 3.2 100BASE-TX Compliance Testing
      1. 3.2.1 Template (Active Output Interface)
      2. 3.2.2 Differential Output Voltage
      3. 3.2.3 Rise and Fall Time
      4. 3.2.4 Waveform Overshoot
      5. 3.2.5 Jitter
      6. 3.2.6 Duty Cycle Distortion
      7. 3.2.7 Return Loss
    3. 3.3 10BASE-Te Compliance Testing
      1. 3.3.1 Link Pulse
      2. 3.3.2 10BASE-Te Standard
        1. 3.3.2.1 TP_IDL
        2. 3.3.2.2 MAU, Internal
        3. 3.3.2.3 Jitter With TPM
        4. 3.3.2.4 Jitter Without TPM
        5. 3.3.2.5 Differential Voltage
        6. 3.3.2.6 Common-Mode Voltage
        7. 3.3.2.7 Return Loss
        8. 3.3.2.8 Harmonic Content
  7. 4How to Tune DP83825 VoD Swing
    1. 4.1 Example of Tuning DP83825 VoD Swing
  8. 5IEEE802.3u Compliance Testing Scripts for the DP8382x
  9. 6References
  10. 7Revision History

5 IEEE802.3u Compliance Testing Scripts for the DP8382x

The 100BASE-Tx Standard script is shown in the following code block.

Table 5-1 100BASE-Tx Standard
Reg 0x1F = 0x8000//Reset PHY
Reg 0x0 = 0x2100//Program DUT to force speed 100BASE-TX mode
Reg 0x19 = 0x21//Program DUT to Forced MDI mode. Set to 4021 for MDIX mode
Reg 0x1F = 0x4000//Restart PHY
Table 5-2 10BASE-Te Link Pulse
Reg 0x1F = 0x8000//Reset PHY
Reg 0x0 = 0x100//Program DUT to force speed 10BASE-Te mode
Reg 0x19 = 0x21//Program DUT to Forced MDI mode. Set to 4021 for MDIX mode
Reg 0x1F =0x4000//Restart PHY
Table 5-3 10BASE-Te Standard (DP83822)
Reg 0x1F = 0x8000//Reset PHY
Reg 0x0 = 0x100//Program DUT to force speed 10BASE-Te mode
Reg 0x19 = 0x21//Program DUT to Forced MDI mode. Set to 4021 for MDIX mode
Reg 0x16 = 0x7108//Programs DUT to generate data and enables analog loopback mode for termination purposes
Reg 0x1F = 0x4000//Restart PHY
Table 5-4 10BASE-Te Standard (DP83825/6)
Reg 0x1F = 0x8000//Reset PHY
Reg 0x0 = 0x100//Program DUT to force speed 10BASE-Te mode
Reg 0x19 = 0x21//Program DUT to Forced MDI mode. Set to 4021 for MDIX mode
Reg 0x16 = 0x7101//Programs DUT to generate data and enables PCS loopback mode
Reg 0x1F = 0x4000//Restart PHY

Table 5-5 10BASE-Te Harmonic Content
Reg 0x1F = 0x8000//Reset PHY
Reg 0x0 = 0x100//Program DUT to force speed 10BASE-Te mode

Reg 0x27 = 0x0013

//Test mode enable with repetitive 1's