SNLA491 August   2025 DP83826AE , DP83826AI

 

  1.   1
  2.   Trademarks
  3. 1DP83826A Application Overview
  4. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS and CEXT
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface Signals (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
          1. 2.2.6.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  5. 3Summary
  6. 4References

2.5.3 Transmitting and Receiving Packets With BIST

The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. BIST can be performed using various loopback modes to isolate any issues to specific parts of the data path. The BIST generates packetized data with variable content and IPG.

If generating and checking packets with the MAC is not possible, use PRBS packet generation and checking functionality to verify the data path.

Perform reverse loopback with PRBS and a working link partner as follows:

  1. Power and connect the PHY to a link partner.
  2. Enable PRBS packet generation on the PHY (write Reg 0x16 to 5000).
  3. Enable reverse loopback on the link partner (for DP83826A link partner, write Reg 0x16 to 0010).
  4. Wait at least one second, then check PRBS lock status on the PHY (read Reg 0x16[11:10]).

If register 0x16[11] is high, the data path through PHY → MDI is valid. If this test does not pass, the issue can be on the PHY's internal data path or the MDI. To verify the internal data path, perform PRBS with analog loopback using the following script. If the internal data path is valid, then the issue is isolated to the MDI (assuming the link partner is working).

Following is an example sequence of register reads and writes to perform BIST with Analog Loopback in 100Mbps:

// Analog Loopback
begin
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 0108 //Select Analog Loopback
030B 3380 //This helps PRBS LOCK
001F 4000 //Soft Reset

0010      // LSB '5' expected. 

0016 3108 //Enables PRBS Checker Config & Packet Generation Enable
          //After you write '3108' the register should Read 3b04. (Bit 11 & 9 go high)
001B 807D //Lock Error Counter's Value
001B
end
//DP83826A Digital Loopback 100Mbps PRBS Packet Generator
begin

0000 2100 //Disable Auto Negotiation and Chooses 100 Mbps
0016 0104 //Enable Digital Loopback
0122 2000 
0123 2000 
0130 47FF 
001F 4000 //Soft Reset

0010      //Bit 0 = '1' confirms Link (No Link expected for 10 Mbps)
          //Bit 1 = '0' confirms 100 Mbps Speed

0016 3104 //Enables PRBS Checker Config & Packet Generation Enable
          //After you write '3104' the register should Read 3b04. (Bit 11 & 9 go high)
001B 807D //Lock Error Counter's Value
001B
end
Note: The best practice is to include a hard reset (Reg 0x0[15]) at the beginning of each script in debugging to make sure prior configurations do not affect results.