SNLA491 August   2025 DP83826AE , DP83826AI

 

  1.   1
  2.   Trademarks
  3. 1DP83826A Application Overview
  4. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS and CEXT
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface Signals (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
          1. 2.2.6.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  5. 3Summary
  6. 4References

2.4.1 MII Check

The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC. The MII is fully compliant with IEEE 802.3-2002 clause 22.

MII is set by default in the PHY with Hardware Strap 8 RX_D2 = '0'. Reg 0x0467[8] can confirm the status of strap 8 (High or Low), and Reg 0x0468[4] can confirm the PHY initial MAC Mode (MII = 0 | RMII = 1).

The MII signals are summarized below:

Table 2-8 MII Signals
FunctionPins
Data SignalsTX_D[3:0]
RX_D[3:0]
Transmit and Receive SignalsTX_EN
RX_DV
Line-Status SignalsCRS
COL
Error SignalsRX_ER
MII SignalingFigure 2-13 MII Signaling

Reference the waveforms below to verify the expected MAC data and clock signals for 100BASE-Tx MII Mode. Table 2-9 displays specs taken from the data sheet shown in the waveforms. MII signaling needs to be 2.5MHz if PHY is not linked up or linked up at 10Mbps, and needs to be at 25MHz if linked at 100Mbps. Note that both TX_CLK and RX_CLK are outputs of the PHY.

If a MAC bus (TX or RX) is suspected to be problematic, probe the lines at the receiver side of the trace, making sure that the receiver's setup and hold times are met, along with VIH/VIL. Typical symptoms of violating these specifications is packet errors at the MAC while the PHY is indicating clean traffic (Reg 0x15).

Table 2-9 100M MII Receive Timing
Test ConditionMINTYPMAXUnit
RX_CLK High / Low Time162024ns
RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising2028ns
Table 2-10 100M MII Transmit Timing
TEST CONDITIONMINTYPMAXUNIT
TX_CLK High / Low Time162024ns
TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK10 ns
TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0ns
Table 2-11 10M MII Receive Timing
TEST CONDITIONMINTYPMAXUNIT
RX_CLK High / Low Time160200240ns
RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising100 300ns
Table 2-12 10M MII Transmit Timing
TEST CONDITIONMINTYPMAXUNIT
TX_CLK High / Low Time190200240ns
TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK25 ns
TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0ns
100M RX_CLK High TimeFigure 2-14 100M RX_CLK High Time
100M RX_D1 Delay From RX_CLK RisingFigure 2-15 100M RX_D1 Delay From RX_CLK Rising