There are several options for loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the MII and MDI data paths. DP83826 can be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback.

MII Loopback is configured using the BMCR (Reg 0x0). All other loopback modes are enabled using the BISCR (Reg 0x16). Loopback modes are supported for all speeds (10/100) and all MAC interfaces.

Figure 2-20 illustrate the various data paths that each loopback mode can be used to verify:

Figure 2-20 Loopback Modes Block Diagram

Figure 2-21 Reverse Loopback Mode Block Diagram

Analog loopback is typically used to verify the PHY's full internal data path, while reverse loopback is used with a link partner to verify the data path along the MDI.

// Digital Loopback

begin
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 0104 //Select Digital Loopback
0122 2000 //This helps PRBS LOCK
0123 2000 //This helps PRBS LOCK
0130 47FF //This helps PRBS LOCK
001F 4000 //Soft Reset
end

// Reverse Loopback

begin
0016 0110 //Select Digital Loopback
001F 4000 //Soft Reset
end