SNLS676 Data sheet

SNLS676A May 2022 – December 2025 DP83TC813R-Q1 , DP83TC813S-Q1

PRODUCTION DATA

8.2 DP83TC813 Registers

Table 8-3 lists the memory-mapped registers for the DP83TC813 registers. All register offset addresses not listed in Table 8-3 should be considered as reserved locations and the register contents should not be modified.

Table 8-3 DP83TC813 Registers

Offset	Acronym	Register Name	Section
0h	BMCR	IEEE Control Register	Section 8.2.1
1h	BMSR	IEEE Status Register	Section 8.2.2
2h	PHYIDR1	PHY Identification Register - 1	Section 8.2.3
3h	PHYIDR2	PHY Identification Register - 2	Section 8.2.4
10h	PHYSTS	PHY Status Register	Section 8.2.5
11h	PHYSCR	Software Control Register	Section 8.2.6
12h	MISR1	Interrupt Register -1	Section 8.2.7
13h	MISR2	Interrupt Register -2	Section 8.2.8
15h	RECR	RX Error Count Register	Section 8.2.9
16h	BISCR	BIST Control Register	Section 8.2.10
18h	MISR3	Interrupt Register -3	Section 8.2.11
19h	REG_19	PHY Address Status Register	Section 8.2.12
1Bh	TC10_ABORT_REG	TC10 Abort Register	Section 8.2.13
1Eh	CDCR	TDR Run Status Register	Section 8.2.14
1Fh	PHYRCR	Reset Control Register	Section 8.2.15
133h	Register_133	CnS Status Register	Section 8.2.16
17Fh	Register_17F	WUR WUP Configuration Register	Section 8.2.17
180h	Register_180	Sleep REQ and ACK Timer Register	Section 8.2.18
181h	Register_181	LPS Received Count Register	Section 8.2.19
182h	Register_182	WUR Received Count Register	Section 8.2.20
183h	LPS_CFG4	Low Power Configuration Register - 4	Section 8.2.21
184h	LPS_CFG	Low Power Configuration Register - 0	Section 8.2.22
185h	LPS_CFG5	Low Power Configuration Register - 5	Section 8.2.23
187h	LPS_CFG7	Low Power Configuration Register - 7	Section 8.2.24
188h	LPS_CFG8	Low Power Configuration Register - 8	Section 8.2.25
189h	LPS_CFG9	Low Power Configuration Register - 9	Section 8.2.26
18Ah	LPS_CFG10	Low Power Configuration Register - 10	Section 8.2.27
18Bh	LPS_CFG2	Low Power Configuration Register - 2	Section 8.2.28
18Ch	LPS_CFG3	Low Power Configuration Register - 3	Section 8.2.29
18Eh	LPS_STATUS	Low Power Status Register	Section 8.2.30
300h	TDR_TX_CFG	TDR TX Configuration Register	Section 8.2.31
301h	TAP_PROCESS_CFG	Tap Process Configuration Register	Section 8.2.32
302h	TDR_CFG1	TDR Configuration Register - 1	Section 8.2.33
303h	TDR_CFG2	TDR Configuration Register - 2	Section 8.2.34
304h	TDR_CFG3	TDR Configuration Register - 3	Section 8.2.35
305h	TDR_CFG4	TDR Configuration Register - 4	Section 8.2.36
306h	TDR_CFG5	TDR Configuration Register - 5	Section 8.2.37
310h	TDR_TC1	TDR Status Register	Section 8.2.38
430h	A2D_REG_48	RGMII ID Control Register	Section 8.2.39
442h	A2D_REG_66	ESD Event Count Register - 1	Section 8.2.40
450h	LEDS_CFG_1	LED Configuration Register - 1	Section 8.2.41
451h	LEDS_CFG_2	LED Configuration Register - 2	Section 8.2.42
452h	IO_MUX_CFG_1	IO Multiplexing Register - 1	Section 8.2.43
453h	IO_MUX_CFG_2	IO Multiplexing Register - 2	Section 8.2.44
456h	IO_MUX_CFG	xMII Impedance Control Register	Section 8.2.45
45Dh	CHIP_SOR_1	Strap Status Register	Section 8.2.46
45Fh	LED1_CLKOUT_ANA_CTRL	CLKOUT and LED_1 Control Register	Section 8.2.47
489h	TX_INTER_CFG	Interleave Configuration Register	Section 8.2.48
496h	JABBER_CFG	Jabber Configuration Register	Section 8.2.49
553h	PG_REG_4	Auto-Polarity Correction Control Register	Section 8.2.50
560h	TC1_CFG_RW	TC1 Configuration Register	Section 8.2.51
561h	TC1_LINK_FAIL_LOSS	TC1 Link Fail Count Register	Section 8.2.52
562h	TC1_LINK_TRAINING_TIME	TC1 Link Training Time Register	Section 8.2.53
563h	NO_LINK_TH		Section 8.2.54
600h	RGMII_CTRL	RGMII Control Register	Section 8.2.55
601h	RGMII_FIFO_STATUS	RGMII FIFO Status Register	Section 8.2.56
602h	RGMII_CLK_SHIFT_CTRL	RGMII Shift Control Register	Section 8.2.57
608h	SGMII_CTRL_1	SGMII Control Register - 1	Section 8.2.58
60Ah	SGMII_STATUS	SGMII Status Register	Section 8.2.59
60Ch	SGMII_CTRL_2	SGMII Control Register - 2	Section 8.2.60
60Dh	SGMII_FIFO_STATUS	SGMII FIFO Status Register	Section 8.2.61
618h	PRBS_STATUS_1	PRBS Status Register - 1	Section 8.2.62
619h	PRBS_CTRL_1	PRBS Control Register - 1	Section 8.2.63
61Ah	PRBS_CTRL_2	PRBS Control Register - 2	Section 8.2.64
61Bh	PRBS_CTRL_3	PRBS Control Register - 3	Section 8.2.65
61Ch	PRBS_STATUS_2	PRBS Status Register - 2	Section 8.2.66
61Dh	PRBS_STATUS_3	PRBS Status Register - 3	Section 8.2.67
61Eh	PRBS_STATUS_4	PRBS Status Register - 4	Section 8.2.68
620h	PRBS_STATUS_5	PRBS Status Register - 5	Section 8.2.69
622h	PRBS_STATUS_6	PRBS Status Register - 6	Section 8.2.70
623h	PRBS_STATUS_7	PRBS Status Register - 7	Section 8.2.71
624h	PRBS_CTRL_4	PRBS Control Register - 4	Section 8.2.72
625h	PATTERN_CTRL_1	BIST Pattern Control Register - 1	Section 8.2.73
626h	PATTERN_CTRL_2	BIST Pattern Control Register - 2	Section 8.2.74
627h	PATTERN_CTRL_3	BIST Pattern Control Register - 3	Section 8.2.75
628h	PMATCH_CTRL_1	BIST Match Control Register - 1	Section 8.2.76
629h	PMATCH_CTRL_2	BIST Match Control Register - 2	Section 8.2.77
62Ah	PMATCH_CTRL_3	BIST Match Control Register - 3	Section 8.2.78
639h	TX_PKT_CNT_1	xMII TX Packet Count Register - 1	Section 8.2.79
63Ah	TX_PKT_CNT_2	xMII TX Packet Count Register - 2	Section 8.2.80
63Bh	TX_PKT_CNT_3	xMII TX Packet Count Register - 3	Section 8.2.81
63Ch	RX_PKT_CNT_1	xMII RX Packet Count Register - 2	Section 8.2.82
63Dh	RX_PKT_CNT_2	xMII RX Packet Count Register - 2	Section 8.2.83
63Eh	RX_PKT_CNT_3	xMII RX Packet Count Register - 3	Section 8.2.84
648h	RMII_CTRL_1	RMII Control Register	Section 8.2.85
649h	RMII_STATUS_1	RMII FIFO Status Register	Section 8.2.86
871h	dsp_reg_71	SQI Register	Section 8.2.87
1000h	MMD1_PMA_CTRL_1		Section 8.2.88
1001h	MMD1_PMA_STATUS_1		Section 8.2.89
1007h	MMD1_PMA_STATUS_2		Section 8.2.90
100Bh	MMD1_PMA_EXT_ABILITY_1		Section 8.2.91
1012h	MMD1_PMA_EXT_ABILITY_2		Section 8.2.92
1834h	MMD1_PMA_CTRL_2		Section 8.2.93
1836h	MMD1_PMA_TEST_MODE_CTRL		Section 8.2.94
3000h	MMD3_PCS_CTRL_1		Section 8.2.95
3001h	MMD3_PCS_Status_1		Section 8.2.96

Complex bit access types are encoded to fit into small table cells. Table 8-4 shows the codes that are used for access types in this section.

Table 8-4 DP83TC813 Access Type Codes

Access Type	Code	Description
Read Type
H	H	Set or cleared by hardware
R	R	Read
RC	R C	Read to Clear
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W0S	W 0S	Write 0 to set
W1S	W 1S	Write 1 to set
WSC	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.2.1 BMCR Register (Offset = 0h) [Reset = 2100h]

BMCR is shown in Table 8-5.

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Table 8-5 BMCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	MII Reset	RH/W1S	0h	1b = Digital in reset and all MII regs (0x0 - 0xF) reset to default 0b = No reset This bit is auto-cleared
14	xMII Loopback	R/W	0h	1b = Enable MII loopback 0b = Disable MII loopback When xMII loopback mode is activated, the transmitted data presented on xMII TXD is looped back to xMII RXD internally. There is no LINK indication generated when xMII loopback is enabled.
13	Speed Select	R	1h	Speed Selection: Always 100-Mbps Speed
12	Auto-Negotiation Enable	R	0h	Auto-Negotiation: Not supported on this device
11	IEEE Power Down Enable	R/W	0h	This bit can be programmed to enter and exit IEEE power down mode This bit provide status when using INT_N as power down pin 0h = Normal mode 1h = Power down mode
10	Isolate	R/W	0h	Isolates the port from the xMII with the exception of the serial management interface 0h = Normal Mode 1h = Enable Isolate Mode
9	RESERVED	R	0h	Reserved
8	Duplex Mode	R	1h	0h = Half duplex 1h = Full duplex
7	RESERVED	R/W	0h	Reserved
6-0	RESERVED	R	0h	Reserved

8.2.2 BMSR Register (Offset = 1h) [Reset = 0061h]

BMSR is shown in Table 8-6.

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Table 8-6 BMSR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	100Base-T4	R	0h	0b = PHY doesn't support 100BASE-T4
14	100Base-X Full Duplex	R	0h	0h = PHY not able to perform full duplex 100Base-X 1h = PHY able to perform full duplex 100Base-X
13	100Base-X Half Duplex	R	0h	0h = PHY not able to perform half duplex 100Base-X 1h = PHY able to perform half duplex 100Base-X
12	10 Mbps Full Duplex	R	0h	0h = PHY not able to operate at 10Mbps in full duplex 1h = PHY able to operate at 10Mbps in full duplex
11	10 Mbps Half Duplex	R	0h	0h = PHY not able to operate at 10Mbps in half duplex 1h = PHY able to operate at 10Mbps in half duplex
10-7	RESERVED	R	0h	Reserved
6	MF Preamble Suppression	R	1h	0h = PHY does not accept management frames with preamble suppressed 1h = PHY accepts management frames with preamble suppressed
5	RESERVED	R	0h	Reserved
4	RESERVED	H	0h	Reserved
3	Auto-Negotiation Ability	R	0h	0h = PHY is not able to perform Auto-Negotiation 1h = PHY is able to perform Auto-Negotiation
2	Link status	R	0h	0h = Link is down 1h = Link is up
1	Jabber detect	H	0h	0h = No jabber condition detected 1h = Jabber condition detected
0	Extended Capability	R	1h	0h = Basic register set capabilities only 1h = Extended register capabilities

8.2.3 PHYIDR1 Register (Offset = 2h) [Reset = 2000h]

PHYIDR1 is shown in Table 8-7.

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Table 8-7 PHYIDR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Organizationally Unique Identifier 1	R	2000h	Unique Identifier for the part

8.2.4 PHYIDR2 Register (Offset = 3h) [Reset = A271h]

PHYIDR2 is shown in Table 8-8.

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Table 8-8 PHYIDR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	Unique Identifier 2	R	28h	Unique Identifier for the part
9-4	Model Number	R	27h	Unique Identifier for the part
3-0	Revision Number	R	1h	Unique Identifier for the part

8.2.5 PHYSTS Register (Offset = 10h) [Reset = 0004h]

PHYSTS is shown in Table 8-9.

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Table 8-9 PHYSTS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	H	0h	Reserved
12	RESERVED	H	0h	Reserved
11	RESERVED	H	0h	Reserved
10	RESERVED	R/W0S	0h	Reserved
9	Descrambler Lock Status (Latch Low)	R/W0S	0h	0h = Descrambler is unlocked at least once 1h = Descrambler is locked
8	RESERVED	R	0h	Reserved
7	Interrupt Pin Status	H	0h	Interrupts pin status, cleared on reading 0x12 0h = Interrupt pin set 1h = Interrupt pin not set
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	H	0h	Reserved
3	MII Loopback Status	R	0h	0h = No MII loopback 1h = MII loopback
2	Duplex Mode Status	R	1h	0h = Half duplex 1h = Full duplex
1	RESERVED	R	0h	Reserved
0	Link Status (Latch Low) Non-Clear on Read	R	0h	Non-Clear on Read Latch Low link status Status is cleared on reading reg0x1 0h = Link is down atleast once 1h = Link is up

8.2.6 PHYSCR Register (Offset = 11h) [Reset = 010Bh]

PHYSCR is shown in Table 8-10.

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Table 8-10 PHYSCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13-12	RESERVED	R/W	0h	Reserved
11	SGMII Soft Reset	R/WSC	0h	SGMII Digital Reset This bit is auto-cleared
10	MAC Isolate for PHY_ADDR 0x00	R/W	0h	MAC Isolate is enabled only if PHY address is 0x00 Reg0x0[10] works for all PHY addresses including 0x00 0h = Normal mode 1h = Isolate mode (No output from PHY to MAC)
9-8	RMII TX FIFO Depth	R/W	1h	0h = 4 nibbles 1h = 5 nibbles 2h = 6 nibbles
7	RESERVED	R/W	0h	Reserved
6-4	RESERVED	R	0h	Reserved
3	Interrupt Polarity	R/W	1h	0h = Active high 1h = Active low
2	Force Interrupt	R/W	0h	1h = Force interrupt pin
1	Interrupts Enable	R/W	1h	0h = Disable interrupts 1h = Enable interrupts
0	Interrupt Pin Configuration	R/W	1h	0h = Configure INT_N pin as power down input pin 1h = Configure INT_N pin is as interrupt output pin

8.2.7 MISR1 Register (Offset = 12h) [Reset = 0000h]

MISR1 is shown in Table 8-11.

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Table 8-11 MISR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	H	0h	Reserved
14	Energy Detect Change Status	H	0h	Status is changed to 1 when there is a change of MDI Energy detection output Status is cleared on read of this register
13	Link Status Change Status	H	0h	Status is changed to 1 when there is a change of link status Status is cleared on read of this register
12	Wake on LAN Status	H	0h	Status is changed to 1 when WOL is received Status is cleared on read of this register
11	ESD Fault Detected Status	H	0h	Status is changed to 1 when ESD fault is detected Status is cleared on read of this register
10	Training Done Status	H	0h	Status is changed to 1 when training is done Status is cleared on read of this register
9	RESERVED	H	0h	Reserved
8	RX Error Counter Half Full Status	H	0h	Status is changed to 1 when RX Error Counter in 0x15 is half full Status is cleared on read of this register
7	RESERVED	R/W	0h	Reserved
6	Energy Detect Change Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
5	Link Status Change Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
4	Wake on LAN Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
3	ESD Fault Detected Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
2	Link Training Completed Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
1	RESERVED	R/W	0h	Reserved
0	RX Error Counter Half Full Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set

8.2.8 MISR2 Register (Offset = 13h) [Reset = 0000h]

MISR2 is shown in Table 8-12.

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Table 8-12 MISR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Under Voltage Status	H	0h	Status is changed to 1 when Under Voltage is detected Status is cleared on read of this register
14	Over Voltage Status	H	0h	Status is changed to 1 when Over Voltage is detected Status is cleared on read of this register
13	RESERVED	H	0h	Reserved
12	RESERVED	H	0h	Reserved
11	RESERVED	H	0h	Reserved
10	Sleep Mode Status	H	0h	Status is changed to 1 when sleep mode has changed Status is cleared on read of this register
9	Data Polarity Change Status	H	0h	Status is changed to 1 when MDI lines polarity change is detected Status is cleared on read of this register
8	Jabber Detect Status	H	0h	Status is changed to 1 when jabber is detected Status is cleared on read of this register
7	Under Voltage Indication	R/W	0h
6	Over Voltage Indication	R/W	0h	1b = Enable indication on INT_N pin if corresponding Interrupt Status is set 0b = Indication is disabled
5	RESERVED	R/W	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2	RESERVED	R/W	0h	Reserved
1	Data Polarity Change Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
0	Jabber Detect Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set

8.2.9 RECR Register (Offset = 15h) [Reset = 0000h]

RECR is shown in Table 8-13.

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Table 8-13 RECR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX Error Count	RC	0h	RX_ER Counter: When a valid carrier is presented (only while RX_DV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in xMII loopback mode. The counter stops when at the maximum count (0xFFFF). When the counter exceeds half-full (0x7FFF), an interrupt is generated. This register is cleared on read.

8.2.10 BISCR Register (Offset = 16h) [Reset = 0100h]

BISCR is shown in Table 8-14.

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Table 8-14 BISCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	PRBS Lock Lost Latch Status	H	0h	0h = PRBS lock never lost 1h = PRBS lock lost at least once
9	RESERVED	R	0h	Reserved
8	Core Power Mode	R	1h	0h = Core is in power down or sleep mode 1h = Core is in normal power mode
7	RESERVED	R	0h	Reserved
6	Data Transmission to MDI in xMII Loopback	R/W	0h	0h = Transmit data on MDI during xMII loopback
5-2	Loopback Mode	R/W	0h	Enable Loopbacks other than PCS loopback. 0x16[1] must be 0 1h = Digital Loopback 2h = Analog Loopback 4h = Reverse Loopback 8h = External Loopback
1	PCS Loopback Enable	R/W	0h	0h = Disable PCS Loopback 1h = Enable PCS Loopback
0	RESERVED	R/W	0h	Reserved

8.2.11 MISR3 Register (Offset = 18h) [Reset = 00X5h]

MISR3 is shown in Table 8-15.

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Table 8-15 MISR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	H	0h	Reserved
14	No Link Status	H	0h	Status is changed to 1 when Link has not been observed within time programmed in 0x563 after training starts Status is cleared on read of this register
13	RESERVED	H	0h	Reserved
12	Power-On Reset Done Status	H	0h	Status is changed to 1 Power-On Reset is done after the the supplies are up Status is cleared on read of this register
11	No Frame Status	H	0h	Status is changed to 1 when No frame is detected until Status is cleared on read of this register
10	RESERVED	H	0h	Reserved
9	RESERVED	H	0h	Reserved
8	RESERVED	H	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	No Link Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
5	RESERVED	R/W	0h	Reserved
4	Power-On Reset Done Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
3	No Frame Indication	R/W	0h	0h = Indication is disabled 1h = Enable indication on INT_N pin if corresponding Interrupt Status is set
2	RESERVED	R/W	0h	Reserved
1	RESERVED	R/W	0h	Reserved
0	RESERVED	R/W	0h	Reserved

8.2.12 REG_19 Register (Offset = 19h) [Reset = 0800h]

REG_19 is shown in Table 8-16.

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Table 8-16 REG_19 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9-5	RESERVED	R	0h	Reserved
4-0	PHY Address	R	0h	PHY Address latched from straps

8.2.13 TC10_ABORT_REG Register (Offset = 1Bh) [Reset = 0000h]

TC10_ABORT_REG is shown in Table 8-17.

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Table 8-17 TC10_ABORT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	Sleep Abort through GPIO	R/W	0h	Enables aborting TC10 using GPIO. One of CLKOUT/LED_1 pins which is being used as an LED can be used to abort 0h = Disable TC10 abort using GPIO 1h = Enable TC10 abort using GPIO
0	Sleep Abort	R/W	0h	loc_sleep_abprt as defined by TC10 standard. Aborts sleep negotiation while in SLEEP_ACK state 0h = Allow TC10 sleep negotiation 1h = Abort TC10 sleep negotiation

8.2.14 CDCR Register (Offset = 1Eh) [Reset = 0000h]

CDCR is shown in Table 8-18.

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Table 8-18 CDCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	TDR Start	RH/W1S	0h	Bit is cleared after TDR run is complete 1h = Start TDR
14	TDR Auto-Run Enable	R/W	0h	0h = Start TDR manually using 0x1E[15] 1h = Start TDR automatically on link down
13-2	RESERVED	R	0h	Reserved
1	TDR Done Status	R	0h	0h = TDR on-going or not initiated 1h = TDR done
0	TDR Fail Status	R	0h	When TDR Done Status is 1, this bit indicates if TDR ran successfully 0h = TDR ran successfully 1h = TDR run failed

8.2.15 PHYRCR Register (Offset = 1Fh) [Reset = 0000h]

PHYRCR is shown in Table 8-19.

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Table 8-19 PHYRCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Hard Reset	RH/W1S	0h	Hardware Reset (Reset digital + register file) This bet is self clearing 0h = Normal Operation 1h = Resets PHY and clears registers. Does not resample the straps.
14	Soft Reset	RH/W1S	0h	0h = Normal Operation 1h = Restart PHY. Resets PHY but does not clear registers. Does not resample the straps. This bit is self cleared.
13	RESERVED	R/W	0h	Reserved
12-8	RESERVED	R/W	0h	Reserved
7	Standby Mode	R/W	0h	0h = Normal operation 1h = Standby mode enabled
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R	0h	Reserved
4-0	RESERVED	R/W	0h	Reserved

8.2.16 Register_133 (Offset = 133h) [Reset = 0000h]

Register_133 is shown in Table 8-20.

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Table 8-20 Register_133 Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Link Up Status	R	0h	Link Up status as defined by CnS
13	PHY Control In Send Data Mode	R	0h	PHY Control In Send Data Status
12	Link Status	R	0h	Link status set by link monitor
11-8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	Descrambler Lock Status	R	0h	0h = Scrambler Not Locked 1h = Scrambler Locked
1	Local Receiver Status	R	0h	0h = Local PHY received link invalid 1h = Local PHY received link valid
0	Remote Receiver Status	R	0h	0h = Remote PHY received link invalid 1h = Remote PHY received link valid

8.2.17 Register_17F (Offset = 17Fh) [Reset = 4028h]

Register_17F is shown in Table 8-21.

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Table 8-21 Register_17F Field Descriptions

Bit	Field	Type	Reset	Description
15	WUR from WAKE pin	R/W	0h	Enable WUR transmission when a pulse is transmitted on WAKE pin 1b = Enable sending WUR Threshold of WAKE pulse width can be configured through 0x17F[7:0]]
14	WUP Enable	R/W	1h	Enable WUP transmission after local wake 1b = WUP transmission is enabled 0b = WUP transmission is disabled This option can be effectively used when PHY powers-up in Standby mode through strap
13-8	RESERVED	R	0h	Reserved
7-0	Wake Pulse Threshold	R/W	28h	Width of WAKE pulse in microseconds required to initiate WUR during an active link

8.2.18 Register_180 (Offset = 180h) [Reset = 0000h]

Register_180 is shown in Table 8-22.

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Table 8-22 Register_180 Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R	0h	Reserved
4-3	Sleep Request Timer Configuration	R/W	0h	0h = 16ms 1h = 4ms 2h = 32ms 3h = 40ms
2	RESERVED	R	0h	Reserved
1-0	Sleep Acknowledge Timer Configuration	R/W	0h	0h = 8ms 1h = 6ms 2h = 24ms 3h = 32ms

8.2.19 Register_181 (Offset = 181h) [Reset = 0000h]

Register_181 is shown in Table 8-23.

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Table 8-23 Register_181 Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	RX LPS Count	R	0h	Indicates number of LPS codes received

8.2.20 Register_182 (Offset = 182h) [Reset = 0000h]

Register_182 is shown in Table 8-24.

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Table 8-24 Register_182 Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	RX WUR Count	R	0h	Indicates number of WUR codes received

8.2.21 LPS_CFG4 Register (Offset = 183h) [Reset = 0000h]

LPS_CFG4 is shown in Table 8-25.

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Table 8-25 LPS_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Send WUP in Disable Transmit State	R/W	0h	Write 1 to this bit to send WUP when PHY control is in DISABLE_TRANSMIT state
14	Force LPS Sleep Enable	R/W	0h	Force control enable for sleep from LPS SM to PHY control SM
13	Force LPS Sleep	R/W	0h	Force value for sleep from LPS SM to PHY control SM
12	Force Enable for TX LPS	R/W	0h	Force enable for TX_LPS
11	Force TX LPS	R/W	0h	Force value for TX_LPS
10	Force LPS Link Control Enable	R/W	0h	Force link control enable to LPS state machine
9	Force LPS Link Control	R/W	0h	Force link control value from LPS state machine
8	Force LPS State Machine Enable	R/W	0h	Force enable for LPS state machine
7	RESERVED	R	0h	Reserved
6-0	Force LPS State Machine Value	R/W	0h	Force value of LPS state machine

8.2.22 LPS_CFG Register (Offset = 184h) [Reset = 0223h]

LPS_CFG is shown in Table 8-26.

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Table 8-26 LPS_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	cfg_reset_wur_cnt_rx_data	R/W	0h	When set, resets the WUR received symbol counter upon receiving data
14-13	RESERVED	R	0h	Reserved
12	cfg_reset_lps_cnt_rx_data	R/W	0h	When set, resets the LPS received symbol counter upon receiving data
11-10	RESERVED	R	0h	Reserved
9	cfg_reset_wur_cnt_tx_data	R/W	1h	When set, resets the transmitted WUR symbols count when sending data
8-7	RESERVED	R	0h	Reserved
6	cfg_reset_lps_cnt_tx_data	R/W	0h	When set, resets the transmitted LPS symbols count when sending data
5	cfg_wake_fwd_en_wup_psv_link	R/W	1h	Control to enable/disable Wake forwarding on WAKE pin when WUP is received when in PASSIVE_LINK mode 0h = Disables wake forwarding 1h = Enables wake forwarding
4	Wake Forward Force	R/W	0h	1b = Force pulse on WAKE pin Pulse Width is confgurable by bits [3:2] The bit is self-cleared
3-2	Wake Forward Pulse Width	R/W	0h	Configures the pulse width on WAKE pin for wake-forwarding 00b: 50µs 01b: 500µs 10b: 2ms 11b: 20ms
1	Wake Forward Enable	R/W	1h	Enable Wake Forwarding on WAKE pin on reception of WUR Command 0h = Enable Wake forwarding 1h = Disable Wake forwarding
0	cfg_wake_fwd_en_wup	R/W	1h	If set, enables doing wake forwarding when WUP symbols are received 0h = Do not do wake forwarding on WAKE pin 1h = Do wake forwarding on WAKE pin

8.2.23 LPS_CFG5 Register (Offset = 185h) [Reset = 0000h]

LPS_CFG5 is shown in Table 8-27.

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Table 8-27 LPS_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	WUP Timer	R/W	0h	Time for which PHY control SM stays in WAKE_TRANSMIT 0h = 1ms 1h = 0.7ms 2h = 1.3ms 3h = 0.85ms 4h = 1.5ms 5h = 2ms 6h = 2.5ms 7h = 3ms
12-4	RESERVED	R	0h	Reserved
3-2	WUR Symbol Gap	R/W	0h	Max gap allowed between two WUR symbols for acknowledgement of WUR
1-0	LPS Symbol Gap	R/W	0h	Max gap allowed between two LPS symbols for acknowledgement of LPS

8.2.24 LPS_CFG7 Register (Offset = 187h) [Reset = 0000h]

LPS_CFG7 is shown in Table 8-28.

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Table 8-28 LPS_CFG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	LPS Stop at Limit	R/W	0h	Configures the device to stop sending LPS codes once done sending the number of codes configured in 0x1879:0 0h = Continues even after reaching limit 1h = Stops after reaching limit
14-8	RESERVED	R	0h	Reserved
9-0	LPS Limit Select	R/W	0h	Indicates number of LPS symbols to be transmitted before tx_lps_done becomes true

8.2.25 LPS_CFG8 Register (Offset = 188h) [Reset = 0080h]

LPS_CFG8 is shown in Table 8-29.

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Table 8-29 LPS_CFG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	WUR Symbol Number	R/W	80h	Indicates number of WUR symbols to be transmitted

8.2.26 LPS_CFG9 Register (Offset = 189h) [Reset = 0040h]

LPS_CFG9 is shown in Table 8-30.

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Table 8-30 LPS_CFG9 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	LPS	R/W	40h	Indicates number of LPS symbols to be received to set lps_recv

8.2.27 LPS_CFG10 Register (Offset = 18Ah) [Reset = 0040h]

LPS_CFG10 is shown in Table 8-31.

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Table 8-31 LPS_CFG10 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9-0	WUR Symbol Number	R/W	40h	Indicates number of WUR symbols to be received to acknowlege WUR and do wake forwarding

8.2.28 LPS_CFG2 Register (Offset = 18Bh) [Reset = 1C4Bh]

LPS_CFG2 is shown in Table 8-32.

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Table 8-32 LPS_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	Stop Sleep Negotiation on Link Down	R/W	1h	1b = Stop Sleep Negotiation if link goes down during negotiation
11	Stop Sleep Negotiation on Activity	R/W	1h	1b = Stop Sleep Negotiation when activity from MAC is observed in SLEEP_ACK state
10	RESERVED	R/W	0h	Reserved
9	RESERVED	R/W	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	RESERVED	R	0h	Ignore on read
6	Autonomous Mode	R/W	1h	1b = PHY entered normal mode on power up 0b = PHY entered standby mode on power up Default value is decided by LED_1 strap This bit is cleared post link up.
5	Transition To Standby	R/W	0h	1b = Enable normal to standby transition on over temperature/over voltage/under voltage 0b = Disable normal to standby transition on over temperature/over voltage/under voltage
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2	RESERVED	R/W	0h	Reserved
1	LPS Sleep Enable	R/W	1h	Enable transition to Standby mode instead of Sleep mode after successful sleep negotiation (refered to as TC10_SBY) 0h = Enter standby after negotiated LPS 1h = Enter sleep after negotiated LPS
0	RESERVED	R/W	0h	Reserved

8.2.29 LPS_CFG3 Register (Offset = 18Ch) [Reset = 0000h]

LPS_CFG3 is shown in Table 8-33.

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Table 8-33 LPS_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8-0	Power State Entry	RH/W1S	0h	1h = Normal command 10h = Standby command

8.2.30 LPS_STATUS Register (Offset = 18Eh) [Reset = 0000h]

LPS_STATUS is shown in Table 8-34.

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Table 8-34 LPS_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	0h	Reserved
6-0	Power State Status	R	0h	1h = Sleep 2h = Standby 4h = Normal

8.2.31 TDR_TX_CFG Register (Offset = 300h) [Reset = 2710h]

TDR_TX_CFG is shown in Table 8-35.

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Table 8-35 TDR_TX_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TDR Transmit Duration	R/W	2710h	TDR transmit duration in µs Default : 10000µs

8.2.32 TAP_PROCESS_CFG Register (Offset = 301h) [Reset = 1703h]

TAP_PROCESS_CFG is shown in Table 8-36.

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Table 8-36 TAP_PROCESS_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12-8	End Tap Index	R/W	17h	End echo coefficient index for peak detect sweep during TDR
7-5	RESERVED	R	0h	Reserved
4-0	Start Tap Index	R/W	3h	Starting echo coefficient index for peak detect sweep during TDR

8.2.33 TDR_CFG1 Register (Offset = 302h) [Reset = 0045h]

TDR_CFG1 is shown in Table 8-37.

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Table 8-37 TDR_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-4	Neighboring Taps Number	R/W	4h	Number of neighboring echo coefficient taps to be considered for calculating local maximum
3-2	Post-Silence State Timer	R/W	1h	0h = 0ms 1h = 10ms 2h = 100ms 3h = 1000ms
1-0	Pre-Silence State Timer	R/W	1h	0h = 0ms 1h = 10ms 2h = 100ms 3h = 1000ms

8.2.34 TDR_CFG2 Register (Offset = 303h) [Reset = 0419h]

TDR_CFG2 is shown in Table 8-38.

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Table 8-38 TDR_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12-8	Tap Index Offset	R/W	4h	Tap index offset of dyamic peak equation, Start Tap Index + 1'b1
7-0	cfg_tdr_filt_init	R/W	19h	Value of peak_th at x=start_tap_index of dynamic peak threshold equation

8.2.35 TDR_CFG3 Register (Offset = 304h) [Reset = 0030h]

TDR_CFG3 is shown in Table 8-39.

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Table 8-39 TDR_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	cfg_tdr_filt_slope	R/W	30h	Slope of dynamic peak threshold equation (0.4)

8.2.36 TDR_CFG4 Register (Offset = 305h) [Reset = 0004h]

TDR_CFG4 is shown in Table 8-40.

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Table 8-40 TDR_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9	RESERVED	R/W	0h	Reserved
8-7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5-4	hpf_gain_tdr	R/W	0h	HPF gain code during TDR
3-0	pga_gain_tdr	R/W	4h	PGA gain code during TDR

8.2.37 TDR_CFG5 Register (Offset = 306h) [Reset = 000Ah]

TDR_CFG5 is shown in Table 8-41.

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Table 8-41 TDR_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3-0	cfg_cable_delay_num	R/W	Ah	Configure the propagation delay per meter of the cable in nanoseconds. This is used for the fault location estimation Valid values : 4 'd0 to 4 'd11 - [4.5:0.1:5.6]ns Default : 4 'd10 (5.5 ns)

8.2.38 TDR_TC1 Register (Offset = 310h) [Reset = 0000h]

TDR_TC1 is shown in Table 8-42.

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Table 8-42 TDR_TC1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	Fault Detect Status	R	0h	0h = No Fault detected in cable 1h = Fault detected in cable
6	Fault Type	R	0h	0h = Short to GND, supply, or between MDI pins 1h = Open. Applicable to both 1-wire and 2-wire open faults
5-0	TDR Fault Location	R	0h	Fault location in meters (Valid only if Fault Detect Status = 1)

8.2.39 A2D_REG_48 Register (Offset = 430h) [Reset = 0770h]

A2D_REG_48 is shown in Table 8-43.

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Table 8-43 A2D_REG_48 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	RESERVED	R/W	0h	Reserved
11-8	RGMII TX Shift Delay	R/W	7h	Controls Internal Delay in RGMII mode in Steps of 312.5ps Delay = ((Bit[11:8] in decimal) + 1) × 312.5 ps
7-4	RGMII RX Shift Delay	R/W	7h	Controls Internal Delay in RGMII mode in Steps of 312.5ps Delay = ((Bit[7:4] in decimal) + 1) × 312.5 ps
3-0	RESERVED	R/W	0h	Reserved

8.2.40 A2D_REG_66 Register (Offset = 442h) [Reset = 0000h]

A2D_REG_66 is shown in Table 8-44.

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Table 8-44 A2D_REG_66 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14-9	ESD Event Count	R	0h	Field gives the number of ESD events on the copper channel
8	RESERVED	R/W	0h	Reserved
7-5	RESERVED	R/W	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3-0	RESERVED	R/W	0h	Reserved

8.2.41 LEDS_CFG_1 Register (Offset = 450h) [Reset = 2610h]

LEDS_CFG_1 is shown in Table 8-45.

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Table 8-45 LEDS_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Disable LED Stretching	R/W	0h	0h = LED pulses are stretched according to the blink rate in 'LED Blink Rate' field 1h = LED pulses are directly connected to RX_DV(for RX activity) and TX_CTRL(for TX Activity)
13-12	LED Blink Rate	R/W	2h	Blink Rate of the LED when configured for activity 0h = 20Hz (50 ms) 1h = 10Hz (100 ms) 2h = 5Hz (200 ms) 3h = 2Hz (500 ms)
11-8	RESERVED	R/W	0h	Reserved
7-4	LED_1 Options	R/W	1h	0h = Link OK 1h = Link OK + blink on TX/RX activity 2h = Link OK + blink on TX activity 3h = Link OK + blink on RX activity 4h = Link OK + 100Base-T1 Leader 5h = Link OK + 100Base-T1 Follower 6h = TX/RX activity with stretch option 7h = Reserved 8h = Reserved 9h = Link lost (remains on until register 0x1 is read) Ah = PRBS error (toggles on error) Bh = XMII TX/RX Error with stretch option
3-0	RESERVED	R/W	0h	Reserved

8.2.42 LEDS_CFG_2 Register (Offset = 451h) [Reset = 0049h]

LEDS_CFG_2 is shown in Table 8-46.

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Table 8-46 LEDS_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	clk_o_gpio_ctrl_3	R/W	0h	MSB of CLKOUT gpio control. This bit provides additional options for configuring CLKOUT If set to 1, the bit changes the effect of clk_o_gpio_ctrl bits of 0x453 Reg 0x453[2:0] controls CLKOUT as follows 0h = pwr_seq_done 1h = loc_wake_req from analog 2h = loc_wake_req to PHY control 3h = tx_lps_done 4h = tx_lps_done_64 5h = tx_lps 6h = pcs rx sm - receiving 7h = pcs tx sm - tx_enable
14	led_1_gpio_ctrl_3	R/W	0h	MSB of LED_1 gpio control. This bit provides additional options for configuring LED_1 If set to 1, the bit changes the effect of led_1_gpio_ctrl bits of 0x452 Reg 0x452[10:8] controls LED_1 as follows 0h = pwr_seq_done 1h = loc_wake_req from analog 2h = loc_wake_req to PHY control 3h = tx_lps_done 4h = tx_lps_done_64 5h = tx_lps 6h = pcs rx sm - receiving 7h = pcs tx sm - tx_enable
13	RESERVED	R/W	0h	Reserved
12-9	RESERVED	R	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	LED_1 Force Enable	R/W	0h	1h = Force 'LED_1 Force Value' on LED_1 pin
4	LED_1 Force Value	R/W	0h	When LED_1 Force Enable is set, this bit decides the output of LED_1 0h = Low 1h = High
3	LED_1 Polarity	R/W	1h	Polarity of LED_1: 0h = Active Low polarity 1h = Active High polarity Default value is decided by the strap on LED_1. If the strap is placed to supply, LED_1 polarity is 0, else LED_1 polarity is 1.
2	RESERVED	R/W	0h	Reserved
1	RESERVED	R/W	0h	Reserved
0	RESERVED	R/W	0h	Reserved

8.2.43 IO_MUX_CFG_1 Register (Offset = 452h) [Reset = 0000h]

IO_MUX_CFG_1 is shown in Table 8-47.

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Table 8-47 IO_MUX_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14-12	led_1_clk_source	R/W	0h	In case clk_out is MUXed to LED_1 IO, this field controls clk_out source: 000b - XI clock 001b - 200M pll clock 010b - 67 MHz ADC clock (recovered) 011b - Free 200MHz clock 100b - 25M MII clock derived from 200M LD clock 101b - 25MHz clock to PLL (XI or XI/2) or POR clock 110b - Core 100 MHz clock 111b - 67 MHz DSP clock (recovered, 1/3 duty cycle)
11	led_1_clk_inv_en	R/W	0h	If led_1_gpio is configured to led_1_clk_source, Selects inversion of clock at led_1_clk_source
10-8	LED_1 Configuration	R/W	0h	Controls the output of LED_1 IO: 2h = WoL 3h = Under-Voltage indication 6h = ESD 7h = Interrupt
7	RESERVED	R/W	0h	Reserved
6-4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2-0	RESERVED	R/W	0h	Reserved

8.2.44 IO_MUX_CFG_2 Register (Offset = 453h) [Reset = 0001h]

IO_MUX_CFG_2 is shown in Table 8-48.

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Table 8-48 IO_MUX_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Enable TX_ER on LED_1	R/W	0h	Configures LED_1 pin to TX_ER
14-9	RESERVED	R	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7-4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2-0	CLKOUT Configuration	R/W	1h	2h = WoL 3h = Under-Voltage indication 6h = ESD 7h = Interrupt

8.2.45 IO_MUX_CFG Register (Offset = 456h) [Reset = 0000h]

IO_MUX_CFG is shown in Table 8-49.

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Table 8-49 IO_MUX_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RX PUPD Value	R/W	0h	When RX pins PUPD force control is enabled, PUPD is controlled by this register 0h = No pull 1h = Pull up 2h = Pull down 3h = Reserved
13	RX PUPD Force Control	R/W	0h	Enables PUPD force control on RX MAC pins 0h = No force control 1h = enables force control
12-11	TX PUPD Value	R/W	0h	When TX pins PUPD force control is enabled, PUPD is controlled by this register 0h = No pull 1h = Pull up 2h = Pull down 3h = Reserved
10	TX PUPD Force Control	R/W	0h	Enables PUPD force control on TX MAC pins 0h = No force control 1h = Enables force control
9-6	RESERVED	R/W	0h	Reserved
5	Impedance Control - RX Pins	R/W	0h	This bit control the IO slew rate of the RX MAC interface pads in MII, RGMII, and RMII mode. Note: Impedance of driver is same regardless of value, RMII is not suitable for slow mode due to timing constraints 0h = Fast Mode (Default) 1h = Slow Mode
4-1	RESERVED	R	0h	Reserved
0	Impedance Control - TX_CLK	R/W	0h	This bit adjusts the slew rate of TX_CLK in MII mode. 0h = Fast Mode (Default) 1h = Slow Mode

8.2.46 CHIP_SOR_1 Register (Offset = 45Dh) [Reset = 0000h]

CHIP_SOR_1 is shown in Table 8-50.

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Table 8-50 CHIP_SOR_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	LED_1 Strap	R	0h	LED_1 strap sampled at power up
12	RX_D3 Strap	R	0h	RX_D3 strap sampled at power up
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RXD3 Strap	R	0h	RX_D3 strap sampled at reset
7	RXD2 Strap	R	0h	RX_D2 strap sampled at power up or reset
6	RXD1 Strap	R	0h	RX_D1 strap sampled at power up or reset
5	RXD0 Strap	R	0h	RX_D0 strap sampled at power up or reset
4	RXCLK Strap	R	0h	RX_CLK strap sampled at power up or reset
3-2	RXER Strap	R	0h	RX_ER strap sampled at power up or reset
1-0	RXDV Strap	R	0h	RX_DV strap sampled at power up or reset

8.2.47 LED1_CLKOUT_ANA_CTRL Register (Offset = 45Fh) [Reset = 000Ch]

LED1_CLKOUT_ANA_CTRL is shown in Table 8-51.

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Table 8-51 LED1_CLKOUT_ANA_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13-5	RESERVED	R	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3-2	LED_1 Mux Control	R/W	3h	0h = 25MHz XI Clock for daisy chaining 1h = TX_TCLK for test modes 3h = Signal Selected by 'CLKOUT Configuration'
1-0	CLKOUT Mux Control	R/W	0h	0h = 25MHz XI Clock for daisy chaining 1h = TX_TCLK for test modes 3h = Signal Selected by 'CLKOUT Configuration'

8.2.48 TX_INTER_CFG Register (Offset = 489h) [Reset = 0001h]

TX_INTER_CFG is shown in Table 8-52.

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Table 8-52 TX_INTER_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	Reserved
2	Force Interleave	R/W	0h	Force interleave on TX
1	TX Interleave Enable	R/W	0h	Enable interleave on TX, if interleave detected on the RX 0h = Interleave on Tx disabled 1h = Interleave on Tx enabled if interleave detected on Rx
0	Interleave Detection Enable	R/W	1h	0h = Disable Interleave Detection 1h = Enable Interleave Detection

8.2.49 JABBER_CFG Register (Offset = 496h) [Reset = 044Ch]

JABBER_CFG is shown in Table 8-53.

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Table 8-53 JABBER_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10-0	Jabber Timeout Count	R/W	44Ch	Jabber timeout count in µs

8.2.50 PG_REG_4 Register (Offset = 553h) [Reset = 0000h]

PG_REG_4 is shown in Table 8-54.

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Table 8-54 PG_REG_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R/W	0h	Reserved
13	Force Receive Polarity Force Enable	R/W	0h	Enable force on polarity 0h = Auto-polarity on MDI 1h = Force polarity on MDI
12	Receive Polarity Force Value	R/W	0h	Polarity force value. Only valid if bit [13] is 1. 0h = Forced Normal polarity 1h = Forced Inverted polarity
11-0	RESERVED	R/W	0h	Reserved

8.2.51 TC1_CFG_RW Register (Offset = 560h) [Reset = 07E4h]

TC1_CFG_RW is shown in Table 8-55.

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Table 8-55 TC1_CFG_RW Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	RESERVED	R/W	0h	Reserved
12-11	Link Status Metric	R/W	0h	Selects following link up signals as defined by C&S 0h = link_up_c_and_s 1h = link_montor_status 2h = (phy_control = SEND_DATA) 3h = comm_ready from TC1 spec
10-5	Link Failure Scenario	R/W	3Fh	Each bit enables logging of link failure in the given scenario: Bit[5] - SQI greater than the value configured in the SQI Threshold register Bit[6] - RCV_JABBER_DET5 - BAD_SSD Bit[7] - LINK_FAILED Bit[8] - RX_ERROR Bit[9] - BAD_END Bit[10] - RESERVED
4-3	Comm Timer Value	R/W	0h	Selects the hysteresis timer value for TC1 comm ready 0h = 2ms 1h = 500µs 2h = 1ms 3h = 4ms
2-0	SQI Threshold	R/W	4h	SQI threshold used to increment Link Failure Count defined by TC1. Whenever SQI becomes worse than the threshold, link failure count (Register 0x0561 bit[9:0]) as defined by TC1 is incremented

8.2.52 TC1_LINK_FAIL_LOSS Register (Offset = 561h) [Reset = 0000h]

TC1_LINK_FAIL_LOSS is shown in Table 8-56.

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Table 8-56 TC1_LINK_FAIL_LOSS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	Link Losses	R	0h	Number of Link Losses as defined in TC1 since last power cycle
9-0	Link Failures	R	0h	Link Failures as defined in TC1 Number of Link Failures (including RX errors, Bad SSD, Bad ESD, Bad SQI) not causing a link down

8.2.53 TC1_LINK_TRAINING_TIME Register (Offset = 562h) [Reset = 0000h]

TC1_LINK_TRAINING_TIME is shown in Table 8-57.

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Table 8-57 TC1_LINK_TRAINING_TIME Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Communication Ready	R	0h	Communication ready as defined in TC1 1h = PHY is ready for communication
14-8	RESERVED	R	0h	Reserved
7-0	Link Training Time	R	0h	Link Training Time measured in milliseconds measured from soft reset

8.2.54 NO_LINK_TH Register (Offset = 563h) [Reset = 0096h]

NO_LINK_TH is shown in Table 8-58.

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Table 8-58 NO_LINK_TH Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	cfg_no_link_timer_th	R/W	96h	If link is not obtained within this amount of time(in milliseconds), interrupt is provided if enabled

8.2.55 RGMII_CTRL Register (Offset = 600h) [Reset = 0030h]

RGMII_CTRL is shown in Table 8-59.

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Table 8-59 RGMII_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	0h	Reserved
6-4	RGMII TX FIFO Half Full Threshold	R/W	3h	RGMII TX sync FIFO half full threshold
3	RGMII Enable	R/W	0h	0h = RGMII disable Default value is latched from straps 1h = RGMII enable
2	Invert RGMII TX Data Lines	R/W	0h	1h = Invert RGMII TXD[3:0] TX_D3 to TX_D0 TX_D2 to TX_D1 TX_D1 to TX_D2 TX_D0 to TX_D3
1	Invert RGMII RX Data Lines	R/W	0h	1h = Invert RGMII RXD[3:0] RX_D3 to RX_D0 RX_D2 to RX_D1 RX_D1 to RX_D2 RX_D0 to RX_D3
0	RESERVED	R/W	0h	Reserved

8.2.56 RGMII_FIFO_STATUS Register (Offset = 601h) [Reset = 0000h]

RGMII_FIFO_STATUS is shown in Table 8-60.

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Table 8-60 RGMII_FIFO_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	RGMII TX FIFO Full Error	R	0h	0h = No empty fifo error This bit is only cleared on device reset 1h = RGMII TX full error has been indicated
0	RGMII TX FIFO Empty Error	R	0h	0h = No empty fifo error This bit is only cleared on device reset 1h = RGMII TX empty error has been indicated

8.2.57 RGMII_CLK_SHIFT_CTRL Register (Offset = 602h) [Reset = 0000h]

RGMII_CLK_SHIFT_CTRL is shown in Table 8-61.

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Table 8-61 RGMII_CLK_SHIFT_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	RGMII RX Shift	R/W	0h	0h = Clock and data are aligned 1h = Clock is internally delayed by value programmed in DLL RX Shift Delay in register 0x430
0	RGMII TX Shift	R/W	0h	0h = Clock and data are aligned 1h = Clock is internally delayed by value programmed in DLL TX Shift Delay in register 0x430

8.2.58 SGMII_CTRL_1 Register (Offset = 608h) [Reset = 007Bh]

SGMII_CTRL_1 is shown in Table 8-62.

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Table 8-62 SGMII_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	SGMII TX Error Disable	R/W	0h	0h = Enable SGMII TX Error indication 1h = Disable SGMII TX Error indication
14	RESERVED	R/W	0h	Reserved
13-10	RESERVED	R/W	0h	Reserved
9	SGMII Enable	R/W	0h	1b = SGMII enable 0b = SGMII disable Default value is latched from straps If both SGMII and RGMII are enabled, SGMII take precedence
8	SGMII TX Polarity Invert	R/W	0h	1b = Invert SGMII RX_D[3:2] polarity
7	SGMII TX Polarity Invert	R/W	0h	1b = Invert SGMII TX_D[1:0] polarity
6-5	RESERVED	R/W	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2-1	SGMII Auto Negotiation Timer	R/W	1h	Selects duration of SGMII Auto-Negotiation timer 0h = 1.6ms 1h = 2µs 2h = 800µs 3h = 11ms
0	SGMII Auto Negotiation Enable	R/W	1h	0h = Disable SGMII Auto-Negotiation 1h = Enable SGMII Auto-Negotaition

8.2.59 SGMII_STATUS Register (Offset = 60Ah) [Reset = 0000h]

SGMII_STATUS is shown in Table 8-63.

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Table 8-63 SGMII_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	SGMII Page Received	R	0h	0h = No new auto neg page received 1h = A new auto neg page received
11	SGMII Link Status	R	0h	0h = SGMII link is down 1h = SGMII link is up
10	SGMII Auto Negotiation Status	R	0h	1h = SGMII autoneg completed
9	Word Boundary Align Indication	R	0h	1h = Aligned
8	Word Boundary Sync Status	R	0h	0h = sync not achieved 1h = sync achieved
7-4	Word Boundary Index	R	0h	Word boundary index selection
3-0	RESERVED	R	0h	Reserved

8.2.60 SGMII_CTRL_2 Register (Offset = 60Ch) [Reset = 0024h]

SGMII_CTRL_2 is shown in Table 8-64.

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Table 8-64 SGMII_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8	SGMII CDR Lock Value	R/W	0h	SGMII CDR lock force value
7	SGMII CDR Lock Force Enable	R/W	0h	SGMII CDR lock force enable
6	SGMII Auto Negotiation Restart	RH/W1S	0h	Restart SGMII autonegotiation
5-3	SGMII TX FIFO Half Full Threshold	R/W	4h	SGMII TX sync FIFO half full threshold
2-0	SGMII RX FIFO Half Full Threshold	R/W	4h	SGMII RX sync FIFO half full threshold

8.2.61 SGMII_FIFO_STATUS Register (Offset = 60Dh) [Reset = 0000h]

SGMII_FIFO_STATUS is shown in Table 8-65.

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Table 8-65 SGMII_FIFO_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R	0h	Reserved
3	SGMII RX FIFO Full Error	H	0h	0h = No error indication 1h = SGMII RX fifo full error has been indicated
2	SGMII RX FIFO Empty Error	H	0h	0h = No error indication 1h = SGMII RX fifo empty error has been indicated
1	SGMII TX FIFO Full Error	H	0h	0h = No error indication 1h = SGMII TX fifo full error has been indicated
0	SGMII TX FIFO Empty Error	H	0h	0h = No error indication 1h = SGMII TX fifo empty error has been indicated

8.2.62 PRBS_STATUS_1 Register (Offset = 618h) [Reset = 0000h]

PRBS_STATUS_1 is shown in Table 8-66.

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Table 8-66 PRBS_STATUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	PRBS Error Overflow Counter	R	0h	Holds number of error counter overflow that received by the PRBS checker. Value in this register is locked when write is done to register prbs_status_6 bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active

8.2.63 PRBS_CTRL_1 Register (Offset = 619h) [Reset = 0574h]

PRBS_CTRL_1 is shown in Table 8-67.

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Table 8-67 PRBS_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	Packet Generation Configuration	R/W	0h	0h = Transmit 1518 byte packets in packet generation mode 1h = Transmit 64 byte packets in packet generation mode
12	Send Packet	RH/W1S	0h	Enables generating MAC packet with fix/incremental data with CRC (pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear) Cleared automatically when pkt_done is set
11	RESERVED	R	0h	Reserved
10-8	PRBS Check Select	R/W	5h	000b : Checker receives from RGMII TX 001b : Checker receives from SGMII TX 010b : Checker receives from RMII RX 011b : Checker receives from MII 101b : Checker receives from Cu RX 110b : Reserved 111b : Reserved
7	RESERVED	R	0h	Reserved
6-4	PRBS Transmit Select	R/W	7h	000b : PRBS transmits to RGMII RX 001b : PRBS transmits to SGMII RX 010b : PRBS transmits to RMII RX 011b : PRBS transmits to MII RX 101b : PRBS transmits to Cu TX 110b : Reserved 111b : Reserved
3	PRBS Count Mode	R/W	0h	0h = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting. 1h = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again
2	PRBS Checker Enable	R/W	1h	Enable PRBS checker (to receive data) To be enabled for counters in 0x63C, 0x63D, 0x63E to work 1h = Enable PRBS checker
1	PRBS Generation Enable	R/W	0h	If 0x619[0] is set, 0h = Transmits non-PRBS packet (PRBS checker is also disabled in this case) 1h = Transmits PRBS packet
0	PRBS or Packet Generation Enable	R/W	0h	0h = Disable packet/PRBS generator 1h = Enable packet/PRBS generator

8.2.64 PRBS_CTRL_2 Register (Offset = 61Ah) [Reset = 05DCh]

PRBS_CTRL_2 is shown in Table 8-68.

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Table 8-68 PRBS_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Packet Length	R/W	5DCh	Sets packet length (in bytes) between the PRBS packets or nonPRBS packets generated

8.2.65 PRBS_CTRL_3 Register (Offset = 61Bh) [Reset = 007Dh]

PRBS_CTRL_3 is shown in Table 8-69.

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Table 8-69 PRBS_CTRL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	PRBS IPG	R/W	7Dh	Sets IPG (in bytes) between the PRBS packets or non-PRBS packets generated

8.2.66 PRBS_STATUS_2 Register (Offset = 61Ch) [Reset = 0000h]

PRBS_STATUS_2 is shown in Table 8-70.

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Table 8-70 PRBS_STATUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Checker Byte Count	R	0h	Holds number of total bytes that received by the PRBS checker. Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFF This counter is cleared if this counter is read after programming 0x620[1]=1

8.2.67 PRBS_STATUS_3 Register (Offset = 61Dh) [Reset = 0000h]

PRBS_STATUS_3 is shown in Table 8-71.

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Table 8-71 PRBS_STATUS_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Checker Packet Count-1	R	0h	Holds Bits [15:0] of number of total packets received by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF This counter is cleared if 0x61D,0x61E are read in the same order after programming 0x620[1]=1

8.2.68 PRBS_STATUS_4 Register (Offset = 61Eh) [Reset = 0000h]

PRBS_STATUS_4 is shown in Table 8-72.

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Table 8-72 PRBS_STATUS_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Checker Packet Count-2	R	0h	Holds Bits [31:16] of number of total packets received by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF This counter is cleared if 0x61D,0x61E are read in the same order after programming 0x620[1]=1

8.2.69 PRBS_STATUS_5 Register (Offset = 620h) [Reset = 0000h]

PRBS_STATUS_5 is shown in Table 8-73.

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Table 8-73 PRBS_STATUS_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	MAC Packet Gen Done	R	0h	Set when all MAC packets with CRC are transmitted 0h = MAC packet transmission in progress 1h = MAC packets transmission completed
11	MAC Packet Gen Busy	R	0h	0h = Packet generator is not in process 1h = Packet generator is in process
10	PRBS Checker Packet Count Overflow Status	R	0h	If PRBS Checker Packet Count overflows, this status bit is set to 1 This overflow status is cleared after clearing PRBS byte counter using 0x620[1]
9	PRBS Checker Byte Count Overflow Status	R	0h	If PRBS Checker Byte Count overflows, this status bit is set to 1 This overflow status is cleared after clearing PRBS byte counter using 0x620[1]
8	PRBS Lock	R	0h	1h = PRBS checker is locked and synced with the received stream
7-0	PRBS Error Count	R	0h	Writing 1 to bit 0 locks all PRBS counters Writing 1 to bit1 locks all PRBS counters and clears the counters on read of those specific registers Bits [1:0] are self-cleared after write Reading Bits[7:0] after writing bit0/bit1, gives the number of error bits received by PRBS checker When PRBS Count Mode set to zero, count stops on 0xFF

8.2.70 PRBS_STATUS_6 Register (Offset = 622h) [Reset = 0000h]

PRBS_STATUS_6 is shown in Table 8-74.

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Table 8-74 PRBS_STATUS_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Packer Error Count-1	R	0h	Holds Bits [15:0] of number of total packets received with error by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF This counter is cleared if 0x622,0x623 are read in the same order after programming 0x620[1]=1

8.2.71 PRBS_STATUS_7 Register (Offset = 623h) [Reset = 0000h]

PRBS_STATUS_7 is shown in Table 8-75.

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Table 8-75 PRBS_STATUS_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS Packer Error Count-2	R	0h	Holds Bits [31:16] of number of total packets received with error by the PRBS checker Value in register is locked when 0x620[0] or 0x620[1] are written When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF This counter is cleared if 0x622,0x623 are read in the same order after programming 0x620[1]=1

8.2.72 PRBS_CTRL_4 Register (Offset = 624h) [Reset = 5511h]

PRBS_CTRL_4 is shown in Table 8-76.

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Table 8-76 PRBS_CTRL_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	MAC Packet Data	R/W	55h	Fixed data to be sent when MAC Packet Mode is set to Fixed mode
7-6	MAC Packet Mode	R/W	0h	0h = Incremental 1h = Fixed 2h = PRBS 3h = PRBS
5-3	Pattern Length in MAC Packets	R/W	2h	Number of bytes of valid pattern in packet (Max - 6)
2-0	Packet Count for MAC Packets Mode	R/W	1h	0h = 1 packet 1h = 10 packets 2h = 100 packets 3h = 1000 packets 4h = 10000 packets 5h = 100000 packets 6h = 1000000 packets 7h = Continuous packets

8.2.73 PATTERN_CTRL_1 Register (Offset = 625h) [Reset = 0000h]

PATTERN_CTRL_1 is shown in Table 8-77.

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Table 8-77 PATTERN_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Pattern in MAC Packets [15:0]	R/W	0h	Bytes 0,1 of programmable pattern in MAC packets

8.2.74 PATTERN_CTRL_2 Register (Offset = 626h) [Reset = 0000h]

PATTERN_CTRL_2 is shown in Table 8-78.

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Table 8-78 PATTERN_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Pattern in MAC Packets [31:16]	R/W	0h	Bytes 2,3 of programmable pattern in MAC packets

8.2.75 PATTERN_CTRL_3 Register (Offset = 627h) [Reset = 0000h]

PATTERN_CTRL_3 is shown in Table 8-79.

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Table 8-79 PATTERN_CTRL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Pattern in MAC Packets [47:32]	R/W	0h	Bytes 4,5 of programmable pattern in MAC packets

8.2.76 PMATCH_CTRL_1 Register (Offset = 628h) [Reset = 0000h]

PMATCH_CTRL_1 is shown in Table 8-80.

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Table 8-80 PMATCH_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Destination Address in MAC Packets [15:0]	R/W	0h	Destination Address field in the generated MAC packets

8.2.77 PMATCH_CTRL_2 Register (Offset = 629h) [Reset = 0000h]

PMATCH_CTRL_2 is shown in Table 8-81.

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Table 8-81 PMATCH_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Destination Address in MAC Packets [31:16]	R/W	0h	Destination Address field in the generated MAC packets

8.2.78 PMATCH_CTRL_3 Register (Offset = 62Ah) [Reset = 0000h]

PMATCH_CTRL_3 is shown in Table 8-82.

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Table 8-82 PMATCH_CTRL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Destination Address in MAC Packets [47:32]	R/W	0h	Destination Address field in the generated MAC packets

8.2.79 TX_PKT_CNT_1 Register (Offset = 639h) [Reset = 0000h]

TX_PKT_CNT_1 is shown in Table 8-83.

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Table 8-83 TX_PKT_CNT_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TX Packet Count [15:0]	RC	0h	Lower 16 bits of TX packets from MAC counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

8.2.80 TX_PKT_CNT_2 Register (Offset = 63Ah) [Reset = 0000h]

TX_PKT_CNT_2 is shown in Table 8-84.

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Table 8-84 TX_PKT_CNT_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TX Packet Count [31:16]	RC	0h	Upper 16 bits of TX packets from MAC counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

8.2.81 TX_PKT_CNT_3 Register (Offset = 63Bh) [Reset = 0000h]

TX_PKT_CNT_3 is shown in Table 8-85.

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Table 8-85 TX_PKT_CNT_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TX Error Packet Count	RC	0h	TX packets from MAC with CRC error counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

8.2.82 RX_PKT_CNT_1 Register (Offset = 63Ch) [Reset = 0000h]

RX_PKT_CNT_1 is shown in Table 8-86.

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Table 8-86 RX_PKT_CNT_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX Packet Count [15:0]	RC	0h	Lower 16 bits of RX packets received from MDI Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

8.2.83 RX_PKT_CNT_2 Register (Offset = 63Dh) [Reset = 0000h]

RX_PKT_CNT_2 is shown in Table 8-87.

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Table 8-87 RX_PKT_CNT_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX Packet Count [31:16]	RC	0h	Upper 16 bits of RX packets received from MDI Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

8.2.84 RX_PKT_CNT_3 Register (Offset = 63Eh) [Reset = 0000h]

RX_PKT_CNT_3 is shown in Table 8-88.

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Table 8-88 RX_PKT_CNT_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX Error Packet Count	RC	0h	Rx packet with error (CRC error) counter Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

8.2.85 RMII_CTRL_1 Register (Offset = 648h) [Reset = 0120h]

RMII_CTRL_1 is shown in Table 8-89.

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Table 8-89 RMII_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	RMII TXD Delay Disable	R/W	0h	If set, disables delay of TXD in RMII mode
9-7	RMII Half Full Threshold	R/W	2h	FIFO Half Full Threshold in nibbles for the RMII Rx FIFO
6	RMII Enable	R/W	0h	1h = RMII Enable
5	RESERVED	R/W	0h	Reserved
4	RMII Follower Enable	R/W	0h	Not recommended to configure this bit. Can be used as a status bit 1h = RMII Follower mode is enabled
3	RESERVED	R/W	0h	Reserved
2	RESERVED	R/W	0h	Reserved
1	RMII Rev1.0 Enable	R/W	0h	1h = Enable RMII rev1.0
0	RMII Enhanced Mode Enable	R/W	0h	1h = Enable RMII Enhanced mode

8.2.86 RMII_STATUS_1 Register (Offset = 649h) [Reset = 0000h]

RMII_STATUS_1 is shown in Table 8-90.

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Table 8-90 RMII_STATUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	0h	Reserved
1	RMII FIFO Empty Error	R	0h	Clear on read bit RMII FIFO underflow error status
0	RMII FIFO Full Error	R	0h	Clear on Read bit RMII FIFO overflow status

8.2.87 dsp_reg_71 Register (Offset = 871h) [Reset = 0000h]

dsp_reg_71 is shown in Table 8-91.

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Table 8-91 dsp_reg_71 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-5	Worst SQI	RC	0h	Worst SQI value since last read
4	RESERVED	R	0h	Reserved
3-1	SQI Value	R	0h	SQI value
0	RESERVED	R	0h	Reserved

8.2.88 MMD1_PMA_CTRL_1 Register (Offset = 1000h) [Reset = 0000h]

MMD1_PMA_CTRL_1 is shown in Table 8-92.

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Table 8-92 MMD1_PMA_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PMA Reset	R/W	0h	1h = PMA reset
14-1	RESERVED	R	0h	Reserved
0	PMA Loopback	R/W	0h	1h = PMA loopback set

8.2.89 MMD1_PMA_STATUS_1 Register (Offset = 1001h) [Reset = 0000h]

MMD1_PMA_STATUS_1 is shown in Table 8-93.

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Table 8-93 MMD1_PMA_STATUS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	Reserved
2	Link Status	R	0h	1h = Link is up
1-0	RESERVED	R	0h	Reserved

8.2.90 MMD1_PMA_STATUS_2 Register (Offset = 1007h) [Reset = 003Dh]

MMD1_PMA_STATUS_2 is shown in Table 8-94.

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Table 8-94 MMD1_PMA_STATUS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5-0	PMA PMD Type Selection	R	3Dh	PMA or PMD type selection field 111101b = 100BASE-T1 PMA or PMD

8.2.91 MMD1_PMA_EXT_ABILITY_1 Register (Offset = 100Bh) [Reset = 0800h]

MMD1_PMA_EXT_ABILITY_1 is shown in Table 8-95.

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Table 8-95 MMD1_PMA_EXT_ABILITY_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	Extended Abilities	R	1h	0h = PMA/PMD does not have extended abilities 1h = PMA/PMD has BASE-T1 extended abilities
10-0	RESERVED	R	0h	Reserved

8.2.92 MMD1_PMA_EXT_ABILITY_2 Register (Offset = 1012h) [Reset = 0001h]

MMD1_PMA_EXT_ABILITY_2 is shown in Table 8-96.

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Table 8-96 MMD1_PMA_EXT_ABILITY_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h	Reserved
0	100BASE-T1 Ability	R	1h	0h = PMA/PMD does not support 100BASE-T1 1h = PMA/PMD supports 100BASE-T1

8.2.93 MMD1_PMA_CTRL_2 Register (Offset = 1834h) [Reset = 8000h]

MMD1_PMA_CTRL_2 is shown in Table 8-97.

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Table 8-97 MMD1_PMA_CTRL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Leader Follower Configuration	R/W	0h	0h = Configure PHY as follower 1h = Configure PHY as leader
13-4	RESERVED	R	0h	Reserved
3-0	Type Selection	R	0h	Type selection field 0h = 100BASE-T1

8.2.94 MMD1_PMA_TEST_MODE_CTRL Register (Offset = 1836h) [Reset = 0000h]

MMD1_PMA_TEST_MODE_CTRL is shown in Table 8-98.

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Table 8-98 MMD1_PMA_TEST_MODE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	Compliance Test Mode	R/W	0h	100BASE-T1 test mode control 000b = Normal mode operation 001b = Test mode 1 010b = Test mode 2 011b = Reserved 100b = Test mode 4 101b = Test mode 5 110b = Reserved 111b = Reserved
12-0	RESERVED	R/W	0h	Reserved

8.2.95 MMD3_PCS_CTRL_1 Register (Offset = 3000h) [Reset = 0000h]

MMD3_PCS_CTRL_1 is shown in Table 8-99.

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Table 8-99 MMD3_PCS_CTRL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PCS Reset	R/W	0h	Reset bit, Self Clear. When write to this bit 1: 1. Reset the registers (not vendor specific) at MMD3/MMD7. 2. Reset brk_top Please note: This register is WSC (write-self-clear) and not read-only
14	PCS Loopback	R/W	0h	This bit is cleared by PCS Reset
13-11	RESERVED	R	0h	Reserved
10	RX Clock Stoppable	R/W	0h	RW, reset value = 1. 1= PHY can stop receiving clock during LPI 0= Clock not stoppable Note: This flop implemented at glue logic
9-0	RESERVED	R	0h	Reserved

8.2.96 MMD3_PCS_Status_1 Register (Offset = 3001h) [Reset = 0000h]

MMD3_PCS_Status_1 is shown in Table 8-100.

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Table 8-100 MMD3_PCS_Status_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	TX LPI Received	R	0h	0h = LPI not received 1h = Tx PCS has received LPI
10	RX LPI Received	R	0h	0h = LPI not received 1h = Rx PCS has received LPI
9	TX LPI Indication	R	0h	0h = PCS is not currently receiving LPI 1h = TX PCS is currently receiving LPI
8	RX LPI Indication	R	0h	0h = PCS is not currently receiving LPI 1h = RX PCS is currently receiving LPI
7	RESERVED	R	0h	Reserved
6	TX Clock Stoppable	R	0h	0h = Clock not stoppable 1h = The MAC can stop the clock during LPI
5-0	RESERVED	R	0h	Reserved