SNLS783A May   2025  – October 2025 DP83826AE , DP83826AI

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Mode Comparison Tables
  6. 5 Pin Configuration and Functions (ENHANCED Mode)
  7. 6 Pin Configuration and Functions (BASIC Mode)
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 8.3.2  Auto-MDIX Resolution
      3. 8.3.3  Energy Efficient Ethernet
        1. 8.3.3.1 EEE Overview
        2. 8.3.3.2 EEE Negotiation
      4. 8.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 8.3.5  Wake-on-LAN Packet Detection
        1. 8.3.5.1 Magic Packet Structure
        2. 8.3.5.2 Magic Packet Example
        3. 8.3.5.3 Wake-on-LAN Configuration and Status
      6. 8.3.6  Low Power Modes
        1. 8.3.6.1 Active Sleep
        2. 8.3.6.2 IEEE Power-Down
        3. 8.3.6.3 Deep Power Down State
      7. 8.3.7  Clock Output
      8. 8.3.8  Media Independent Interface (MII)
      9. 8.3.9  Reduced Media Independent Interface (RMII)
      10. 8.3.10 RMII Repeater Mode
      11. 8.3.11 Serial Management Interface
        1. 8.3.11.1 Extended Register Space Access
        2. 8.3.11.2 Write Address Operation
        3. 8.3.11.3 Read Address Operation
        4. 8.3.11.4 Write (No Post Increment) Operation
        5. 8.3.11.5 Read (No Post Increment) Operation
        6. 8.3.11.6 Example Write Operation (No Post Increment)
      12. 8.3.12 100BASE-TX
        1. 8.3.12.1 100BASE-TX Transmitter
          1. 8.3.12.1.1 Code-Group Encoding and Injection
          2. 8.3.12.1.2 Scrambler
          3. 8.3.12.1.3 NRZ to NRZI Encoder
          4. 8.3.12.1.4 Binary to MLT-3 Converter
        2. 8.3.12.2 100BASE-TX Receiver
      13. 8.3.13 10BASE-Te
        1. 8.3.13.1 Squelch
        2. 8.3.13.2 Normal Link Pulse Detection and Generation
        3. 8.3.13.3 Jabber
        4. 8.3.13.4 Active Link Polarity Detection and Correction
      14. 8.3.14 Loopback Modes
        1. 8.3.14.1 Near-end Loopback
        2. 8.3.14.2 MII Loopback
        3. 8.3.14.3 PCS Loopback
        4. 8.3.14.4 Digital Loopback
        5. 8.3.14.5 Analog Loopback
        6. 8.3.14.6 Far-End (Reverse) Loopback
      15. 8.3.15 BIST Configurations
      16. 8.3.16 Cable Diagnostics
        1. 8.3.16.1 Time Domain Reflectometry (TDR)
      17. 8.3.17 Fast Link-Drop Functionality
      18. 8.3.18 LED and GPIO Configuration
    4. 8.4 Programming
      1. 8.4.1 Hardware Bootstraps Configuration
        1. 8.4.1.1 Bootstrap Configurations (ENHANCED Mode)
        2. 8.4.1.2 Strap Configuration (BASIC Mode)
    5. 8.5 Register Maps
      1. 8.5.1 DP83826A Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 9.2.2 Transformer Recommendations
      3. 9.2.3 Capacitive DC Blocking
      4. 9.2.4 Design Requirements
        1. 9.2.4.1 Clock Requirements
          1. 9.2.4.1.1 Oscillator
          2. 9.2.4.1.2 Crystal
      5. 9.2.5 Detailed Design Procedure
        1. 9.2.5.1 MII Layout Guidelines
        2. 9.2.5.2 RMII Layout Guidelines
        3. 9.2.5.3 MDI Layout Guidelines
      6. 9.2.6 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Transformer Layout
        4. 9.4.1.4 Metal Pour
        5. 9.4.1.5 PCB Layer Stacking
          1. 9.4.1.5.1 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.5 Electrical Characteristics

Over operating free-air temperature range  with VDDA3V3 = 3.3V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IEEE Tx Conformance (100BaseTx)
VOD Differential output voltage 950   1050 mV
IEEE Tx Conformance (10BaseTe)
VOD Output differential voltage (2) 1.54 1.75 1.96 V
Power consumption Baseline (Active mode, 50% Traffic, Packet Size : 1518, Random Content, 150 meter Cable)
I(VDDA3V3=3V3) MII (100BaseTx) 45 53 mA
MII (10BaseTe) 35 46 mA
RMII leader (100BaseTx) 45 53 mA
RMII leader (10BaseTe) 35 46 mA
RMII follower (100BaseTx) 45 53 mA
RMII follower (10BaseTe) 35 46 mA
I(VDDIO=3V3) MII (100BaseTx) 8 14 mA
MII (10BaseTe) 5 12 mA
RMII leader (100BaseTx) 9 14 mA
RMII leader (10BaseTe) 9 12 mA
RMII follower (100BaseTx) 7 8.5 mA
RMII follower (10BaseTe) 5 6 mA
I(VDDIO=1V8) MII (100BaseTx) 5 7 mA
MII (10BaseTe) 3 6 mA
RMII leader (100BaseTx) 5 7 mA
RMII leader (10BaseTe) 5 6 mA
RMII follower (100BaseTx) 3 6 mA
RMII follower (10BaseTe) 2 4 mA
Power consumption ( Active mode worst case, 100% Traffic, Packet Size : 1518, Random Content, 150 meter Cable)
I(VDDA3V3=3V3) MII (100BaseTx) 44 55 mA
MII (10BaseTe) 35 48 mA
RMII leader (100BaseTx) 44 55 mA
RMII leader (10BaseTe) 35 48 mA
RMII follower (100BaseTx) 44 55 mA
RMII follower (10BaseTe) 35 48 mA
I(VDDIO=3V3) MII (100BaseTx) 11 15 mA
MII (10BaseTe) 5 12 mA
RMII leader (100BaseTx) 10 15 mA
RMII leader (10BaseTe) 9 12 mA
RMII follower (100BaseTx) 7 12 mA
RMII follower (10BaseTe) 5 10 mA
I(VDDIO=1V8) MII (100BaseTx) 6 9 mA
MII (10BaseTe) 2 6 mA
RMII leader (100BaseTx) 6 9 mA
RMII leader (10BaseTe) 5 7 mA
RMII follower (100BaseTx) 4 8 mA
RMII follower (10BaseTe) 2 6 mA
Power Consumption (Low power modes)
I(AVDD3V3=3V3) 100 BaseTx EEE mode 100 BaseTx link in EEE mode with LPIs ON 15 mA
I(AVDD3V3=3V3) IEEE Power Down 11 mA
Active Sleep 18 mA
RESET 12.5 mA
I(VDDIO=3V3) 100 BaseTx EEE mode 100 BaseTx link in EEE mode with LPIs ON 6 mA
I(VDDIO=3V3) IEEE Power Down 10.5 mA
Active Sleep 10.5 mA
RESET 10.5 mA
I(VDDIO=1V8) 100 BaseTx EEE mode 100 BaseTx link in EEE mode with LPIs ON 4 mA
I(VDDIO=1V8) IEEE Power Down 5.5 mA
Active Sleep 5.5 mA
RESET 5.5 mA
Bootstrap DC Characteristics (2 Level)
VIH_3v3 High level bootstrap threshold : 3V3 1.3 V
VIL_3v3 Low level bootstrap threshold : 3V3 0.6 V
VIH_1v8 High level bootstrap threshold:1V8 1.3 V
VIL_1v8 Low level bootstrap threshold :1V8 0.6 V
Crystal oscillator
COSC_EXT External load capacitance 15 30 pF
IO
VIH_3V3 High level input voltage VDDIO = 3.3V ±10% 1.7 V
VIL_3V3 Low level input voltage VDDIO = 3.3V ±10% 0.8 V
VOH_3V3 High level output voltage IOH = –2mA, VDDIO = 3.3V ±10% 2.4 V
VOL_3V3 Low level output voltage IOL = 2mA, VDDIO = 3.3V ±10% 0.4 V
VIH_1V8 High level input voltage VDDIO = 1.8V ±10% 0.65 x VDDIO  V
VIL_1V8 Low level input voltage VDDIO = 1.8V ±10% 0.35 x VDDIO  V
VOH_1V8 High level output voltage IOH = –2mA, VDDIO = 1.8V ±10% VDDIO –
0.45		 V
VOL_1V8 Low level output voltage IOL = 2mA, VDDIO = 1.8V ±10% 0.45 V
IIH Input high current TA = –40℃ to 85℃, VIN=VDDIO  15 µA
TA = –40℃ to 105℃, VIN=VDDIO  25  µA
IIL Input low current TA = –40℃ to 85℃, VIN=GND  15 µA
TA = –40℃ to 105℃, VIN=GND  25  µA
IOZH Tri-state output high current TA =  –40℃ to 85℃ –15  15 µA
TA =  –40℃ to 105℃ –25  25  µA
IOZL Tri-state output low current TA =  –40℃ to 85℃ –15 15 µA
TA =  –40℃ to 105℃ –25 25 µA
RPD Internal pull down resistor 7.5 10 12.5 kΩ
RPU Internal pull up resistor 7.5 10 12.5 kΩ
CIN Input capacitance XI pin 1 pF
Input pins 5 pF
COUT Output capacitance XO pin 1 pF
Output pins 5 pF
VCM-OSC XI input osc clock common mode voltage VDDIO = 1.8V 0.9 V
VDDIO = 3.3V 1.65 V
Rseries Integrated MAC series termination resistor RX_D[3:0], RX_ER, RX_DV, RX_CLK, TX_CLK 50 Ω
(1) Verified by production test, characterization or design
(2) Requires register 0x030E to program to 0x4A40