SNOSDG7A May   2025  – March 2026 TPS7H6101-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Measurement
    2. 7.2 Deadtime Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gate Drive Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging Methods
          1. 8.3.3.1.1 Internal Bootstrap Charging
          2. 8.3.3.1.2 Direct VIN Bootstrap Charging
          3. 8.3.3.1.3 Dual Bootstrap Charging
          4. 8.3.3.1.4 Two Switch Common Ground Reference
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  PWM_LI and EN_HI
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative Switch Node Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitor
          1. 9.2.2.1.1 Bootstrap Capacitor
          2. 9.2.2.1.2 Input Capacitance
          3. 9.2.2.1.3 Internal Regulator Capacitor
        2. 9.2.2.2 Bootstrap Diode
      3. 9.2.3 Application Results
      4. 9.2.4 Double Pulse Characteristics
        1. 9.2.4.1 Double Pulse Testing Measurement
        2. 9.2.4.2 Double Pulse Testing Results
      5. 9.2.5 Thermal Characteristics
        1. 9.2.5.1 Foster RC Thermal Model
        2. 9.2.5.2 Applying Foster Thermal Networks
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Vias
        2. 9.4.1.2 HVIN Plane
        3. 9.4.1.3 Solder Mask Defined Pads
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
9.2.2.1.1 Bootstrap Capacitor

The external bootstrap capacitor needs to maintain operation above the BOOT UVLO falling threshold during normal operation. As a best design practice, size the capacitor to allow for substantial margin above the BOOT UVLO falling threshold. The first step in determining the bootstrap capacitor value is calculating ∆VBOOT. This is the maximum allowable drop on the bootstrap capacitor:

Equation 10. ΔVBOOT≅VIN- n×VF-VBOOTUVLO=12V-1×0.9V-6.65V=4.35V

where:

  • n is the number of bootstrap diodes used in series
  • VF is the voltage drop of the bootstrap diode chosen
  • VBOOT_UVLO is the BOOT UVLO falling threshold voltage

To maintain significant margin and account for any additional voltage drop across the bootstrap resistor used and also for load transients, the capacitor is calculated for a ∆VBOOT of 1.5V. Referring to the Section 8.3.3.2 section, the value of Qtotal needs to first be determined, and then CBOOT can subsequently be calculated:

Equation 11. Qtotal=Qg+IQBG×DMaxfSW+IQHSfSW=5nC+50µs×0.28100kHz+5mA100kHz=55nC
Equation 12. CBOOT≥ QtotalΔVBOOT=55nC1.5V=36.7nF

A minimum value of 36.7nF is needed for the design. However, given the potential for capacitance changes with temperature and applied voltage, as well as unexpected circuit behavior such as load transients that impact the bootstrap charging time, a 100nF X7R capacitor is selected.