SNVS983C April   2024  – November 2025 TPS7H4011-SEP , TPS7H4011-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics - Ceramic (CFP) Package
    7. 7.7 Electrical Characteristics - Plastic (HTSSOP) Package
    8. 7.8 Quality Conformance Inspection
    9. 7.9 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 9.3.2  Voltage Reference
      3. 9.3.3  Remote Sensing and Setting VOUT
        1. 9.3.3.1 Minimum Output Voltage
        2. 9.3.3.2 Maximum Output Voltage
      4. 9.3.4  Enable
      5. 9.3.5  Fault Input (FAULT)
      6. 9.3.6  Power Good (PWRGD)
      7. 9.3.7  Adjustable Switching Frequency and Synchronization
        1. 9.3.7.1 Internal Clock Mode
        2. 9.3.7.2 External Clock Mode
        3. 9.3.7.3 Primary-Secondary Synchronization
      8. 9.3.8  Turn-On Behavior
        1. 9.3.8.1 Soft-Start (SS_TR)
        2. 9.3.8.2 Safe Start-Up Into Prebiased Outputs
        3. 9.3.8.3 Tracking and Sequencing
      9. 9.3.9  Protection Modes
        1. 9.3.9.1 Overcurrent Protection
          1. 9.3.9.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 9.3.9.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 9.3.9.1.3 COMP Shutdown
          4. 9.3.9.1.4 Low-Side Overcurrent Sinking Protection
        2. 9.3.9.2 Output Overvoltage Protection (OVP)
        3. 9.3.9.3 Thermal Shutdown
      10. 9.3.10 Error Amplifier and Loop Response
        1. 9.3.10.1 Error Amplifier
        2. 9.3.10.2 Power Stage Transconductance
        3. 9.3.10.3 Slope Compensation
        4. 9.3.10.4 Frequency Compensation
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Operating Frequency
        2. 10.2.2.2  Output Inductor Selection
        3. 10.2.2.3  Output Capacitor Selection
        4. 10.2.2.4  Input Capacitor Selection
        5. 10.2.2.5  Soft-Start Capacitor Selection
        6. 10.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 10.2.2.7  Output Voltage Feedback Resistor Selection
        8. 10.2.2.8  Output Voltage Accuracy
        9. 10.2.2.9  Slope Compensation Requirements
        10. 10.2.2.10 Compensation Component Selection
        11. 10.2.2.11 Schottky Diode
      3. 10.2.3 Application Curve
      4. 10.2.4 Parallel Operation Compensation
      5. 10.2.5 Inverting Buck-Boost
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1000 V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±500
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.