SNVS983C April   2024  – November 2025 TPS7H4011-SEP , TPS7H4011-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Device Options Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics - Ceramic (CFP) Package
    7. 7.7 Electrical Characteristics - Plastic (HTSSOP) Package
    8. 7.8 Quality Conformance Inspection
    9. 7.9 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 9.3.2  Voltage Reference
      3. 9.3.3  Remote Sensing and Setting VOUT
        1. 9.3.3.1 Minimum Output Voltage
        2. 9.3.3.2 Maximum Output Voltage
      4. 9.3.4  Enable
      5. 9.3.5  Fault Input (FAULT)
      6. 9.3.6  Power Good (PWRGD)
      7. 9.3.7  Adjustable Switching Frequency and Synchronization
        1. 9.3.7.1 Internal Clock Mode
        2. 9.3.7.2 External Clock Mode
        3. 9.3.7.3 Primary-Secondary Synchronization
      8. 9.3.8  Turn-On Behavior
        1. 9.3.8.1 Soft-Start (SS_TR)
        2. 9.3.8.2 Safe Start-Up Into Prebiased Outputs
        3. 9.3.8.3 Tracking and Sequencing
      9. 9.3.9  Protection Modes
        1. 9.3.9.1 Overcurrent Protection
          1. 9.3.9.1.1 High-Side 1 Overcurrent Protection (HS1)
          2. 9.3.9.1.2 High-Side 2 Overcurrent Protection (HS2)
          3. 9.3.9.1.3 COMP Shutdown
          4. 9.3.9.1.4 Low-Side Overcurrent Sinking Protection
        2. 9.3.9.2 Output Overvoltage Protection (OVP)
        3. 9.3.9.3 Thermal Shutdown
      10. 9.3.10 Error Amplifier and Loop Response
        1. 9.3.10.1 Error Amplifier
        2. 9.3.10.2 Power Stage Transconductance
        3. 9.3.10.3 Slope Compensation
        4. 9.3.10.4 Frequency Compensation
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Operating Frequency
        2. 10.2.2.2  Output Inductor Selection
        3. 10.2.2.3  Output Capacitor Selection
        4. 10.2.2.4  Input Capacitor Selection
        5. 10.2.2.5  Soft-Start Capacitor Selection
        6. 10.2.2.6  Rising VIN Set Point (Configurable UVLO)
        7. 10.2.2.7  Output Voltage Feedback Resistor Selection
        8. 10.2.2.8  Output Voltage Accuracy
        9. 10.2.2.9  Slope Compensation Requirements
        10. 10.2.2.10 Compensation Component Selection
        11. 10.2.2.11 Schottky Diode
      3. 10.2.3 Application Curve
      4. 10.2.4 Parallel Operation Compensation
      5. 10.2.5 Inverting Buck-Boost
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

7.5 Electrical Characteristics

Over 4.5V ≤ VIN ≤ 14V, PVIN = VIN, VSNS- = 0V,  open loop configuration, IOUT = 0A, over operating temperature range (TA = –55°C to 125°C), unless otherwise noted; includes RLAT at TA = 25°C if sub-group number is present for QML RHA and SEP devices(1)
PARAMETER TEST CONDITIONS SUB-GROUP(2) MIN TYP MAX UNIT
POWER SUPPLIES AND CURRENTS
VUVLOR_PVIN PVIN internal UVLO rising threshold 1, 2, 3 3.2 3.4 3.6 V
VUVLOHYST_PVIN PVIN internal UVLO hysteresis 1, 2, 3 425 450 500 mV
VUVLOR_VIN VIN internal UVLO rising threshold 1, 2, 3 3.4 3.6 3.8 V
VUVLOHYST_VIN VIN internal UVLO hysteresis 1, 2, 3 140 155 170 mV
ISHDN_VIN VIN shutdown supply current VEN = 0V VIN = 4.5V 1, 2, 3 2 2.9 mA
VIN = 14V 1, 2, 3 2 3
ISHDN_PVIN PVIN shutdown supply current VEN = 0V PVIN = 4.5V 1, 2, 3 2.6 3.5 mA
PVIN = 14V 1, 2, 3 3.5 4.7
IQ_VIN VIN operating quiescent current (non switching) VEN = 7V, VSENSE = 1V(3) 1, 2, 3 2.6 5 mA
ENABLE AND FAULT
VEN(rising) Enable rising threshold (turn-on) 1, 2, 3 0.555 0.61 0.655 V
VEN(falling) Enable falling threshold (turn-off) 1, 2, 3 0.455 0.51 0.554
tEN(delay) Enable propagation delay EN high to SW high, SS pin open 1, 2, 3 52 100 µs
IEN(LKG) Enable input leakage current VEN = 7V 1, 2, 3 2 100 nA
VFAULT(rising) FAULT threshold rising (turn-off) 1, 2, 3 0.555 0.6 0.635 V
VFAULT(falling) FAULT threshold falling (turn-on) 1, 2, 3 0.455 0.5 0.535
VFAULT(HYS) FAULT hysteresis voltage 1, 2, 3 90 100 110 mV
IFAULT(LKG) Fault input leakage current VFAULT = 7V 1, 2, 3 3 5 µA
tFAULT(min) FAULT minimum pulse width see Figure 8-1 9, 10, 11 0.4 1.4 µs
tFAULT(delay) FAULT delay duration see Figure 8-1 9, 10, 11 26 31 44 (1/fsw) s
VOLTAGE REFERENCE AND REMOTE SENSE
VBG Bandgap voltage (voltage at the REFCAP pin) CREFCAP = 470nF 1, 2, 3 1.184 1.2 1.222 V
IVSNS+(LKG) VSNS+ input leakage current  VSNS+ = 0.6V 1, 2, 3 10 30 nA
IVSNS- VSNS- output current  1, 2, 3 8 10 12 µA
ERROR AMPLIFIER
VIO Error amplifier input offset voltage VSENSE = 0.6V(3) 1, 2, 3 –2.9 2.9 mV
gmEA Error amplifier transconductance –10μA < ICOMP < 10μA, VCOMP = 1V TA = –55℃ 11 1400 2050 2700 µS
TA = 25℃ 9 1200 1650 2100
TA = 125℃ 10 1000 1250 1500
EADC Error amplifier DC gain VSENSE = 0.6V(3) 11500 V/V
EAISRC Error amplifier source VCOMP = 1V, 100mV input overdrive 1, 2, 3 90 125 200 µA
EAISNK Error amplifier sink 90 125 200
EARo Error amplifier output resistance 7 MΩ
EABW Error amplifier bandwidth 9 MHz
OVERCURRENT PROTECTION
IOC_LS(sink) Low-side switch sinking overcurrent threshold TA = –55°C 3 1.6 2.3 3.6 A
TA = 25°C 1 1.5 2.2 3.3
TA = 125°C 2 1.4 2 2.8
IILIM(lkg) ILIM input leakage current ILIM = 7V 1, 2, 3 2 100 nA
COMPSHDN COMP shutdown voltage 1, 2, 3 1.7 1.9 2.1 V
tCOMP(delay) COMP shutdown delay 30 µs
SOFT START AND TRACKING
tSS Soft start time VSS_TR from 10% to 90%, VSNS- = GND,
VOUT(set) = 3.3V		 CSS = 5.6nF 9, 10, 11 1.5 ms
CSS = 22nF 9, 10, 11 4.7 5.8 7.3
CSS = 100nF 9, 10, 11 24.7
RSS(discharge) Soft start discharge pull-down resistor 1, 2, 3 200 442 700 Ω
SSstartup Maximum voltage on SS before startup(4) 20 mV
SLOPE COMPENSATION
SC Slope compensation with 18.3A (typ) current limit fSW = 100kHz,
ILIM = AVDD		 RSC = 1.1MΩ –0.7 A/µs
fSW = 500kHz,
ILIM = AVDD		 RSC = 80.6kΩ –8.8
RSC = 196kΩ –4.2
RSC = 1.1MΩ –1.2
fSW = 1000kHz,
ILIM = AVDD		 RSC = 80.6kΩ –10.5
RSC = 196kΩ –5.1
RSC = 1.1MΩ –2.1
SC Slope compensation with 13.4A (typ) current limit fSW = 500kHz,
RILIM_TOP = 49.9kΩ,
RILIM_BOT = 100kΩ		 RSC = 196kΩ –3.2 A/µs
Slope compensation with 9A (typ) current limit fSW = 500kHz,
RILIM_TOP = 100kΩ,
RILIM_BOT = 49.9kΩ		 RSC = 196kΩ –2.4 A/µs
Slope compensation with 5.6A (typ) current limit fSW = 500kHz,
ILIM = GND		 RSC = 196kΩ –1.8 A/µs
MINIMUM ON TIME AND DEAD TIME
ton(min) Minimum on time 50% to 50% of VIN,
ISW = 2A		 VIN = 4.5V 9, 10, 11 210 235 ns
VIN = 5V 9, 10, 11 213 250
VIN = 12V 9, 10, 11 199 250
VIN = 14V 9, 10, 11 199 250
toff(min) Minimum off time ISW = 2A 306 ns
tdead Dead time 70 ns
SWITCHING FREQUENCY AND SYNCHRONIZATION
fSW RT programmed switching frequency RRT = 511kΩ 4, 5, 6 90 100 120 kHz
RRT = 90.9kΩ 4, 5, 6 450 500 550
RRT = 40.2kΩ VIN = 4.5V 4, 5, 6 850 1000 1150
5 ≤ VIN ≤ 14 4, 5, 6 870 1000 1170
tSYNC_R SYNC1, SYNC2 out low-to-high rise time (10% to 90%) SYNCM = GND, Cload = 25pF,
see Figure 8-3		 9, 10, 11 10 21 ns
tSYNC_F SYNC1, SYNC2 out high-to-low fall time (90% to 10%) SYNCM = GND, Cload = 25pF,
see Figure 8-3		 9, 10, 11 10 21 ns
SYNCPH_2_1 SYNC2 to SYNC1 rising edge phase shift SYNCM = GND, see Figure 8-4 9, 10, 11 82 90 98 °
tSYNC_D SYNC1 to SW delay Non-inverted SYNC1 input (SYNC2 = AVDD,
SYNCM = AVDD), see Figure 8-5		 VIN = 4.5V 9, 10, 11 140 225 350 ns
5V ≤ VIN ≤ 14V 9, 10, 11 120 210 270
VIN = 12V,
IOUT = 12A		 224
Inverted SYNC1 input
(SYNC2 = GND,
SYNCM = AVDD), see Figure 8-6		 VIN = 4.5V 9, 10, 11 150 256 390 ns
5V ≤ VIN ≤ 14V 9, 10, 11 140 240 300
VIN = 12V,
IOUT = 12A		 246
SYNC1 output
(SYNCM = GND), see Figure 8-7		 VIN = 4.5V 9, 10, 11 110 180 280 ns
5V ≤ VIN ≤ 14V 9, 10, 11 90 175 250
VIN = 12V,
IOUT = 12A		 184
VSYNCx(OH) SYNC1, SYNC2 output high SYNCM = GND,
IOH = 2mA		 4.5V ≤ VIN ≤ 5V 1, 2, 3 VIN–0.3 V
VIN > 5V 1, 2, 3 4.5 5 5.2
VSYNCx(OL) SYNC1, SYNC2 output low SYNCM = GND, IOL = 2mA 1, 2, 3 0.4 V
VSYNC1(IH) SYNC1 input high threshold SYNCM = AVDD  1, 2, 3 1.7 V
VSYNC1(IL) SYNC1 input low threshold SYNCM = AVDD 1, 2, 3 0.7
fSYNC SYNC1 input frequency range SYNCM = AVDD 4, 5, 6 100 1000 kHz
DSYNC SYNC1 input duty cycle range SYNCM = AVDD, external clock duty cycle 4, 5, 6 40% 60%
tCLK_E_I External clock to internal clock detection time SYNCM = AVDD, RT populated 9, 10, 11 2 5 (1/fsw) s
tCLK_I_E Internal clock to external clock detection time SYNCM = AVDD, RT populated 9, 10, 11 1 2 (1/fsw) s
POWER GOOD AND THERMAL SHUTDOWN
PWRGDLOW_F% PWRGD falling threshold (fault), low Threshold for PWRGD (VSENSE(3) as percent of VREF), VSNS- = 0V VSENSE falling 1, 2, 3 90% 92% 95%
PWRGDLOW_R% PWRGD rising threshold (good), low VSENSE rising 1, 2, 3 93% 95% 98%
PWRGDHIGH_R% PWRGD rising threshold (fault), high VSENSE rising 1, 2, 3 106% 108% 112%
PWRGDHIGH_F% PWRGD falling threshold (good), high VSENSE falling 1, 2, 3 103% 105% 109%
IPWRGD(LKG) Output high leakage VSENSE = VREF, VPWRGD = 7V 1, 2, 3 50 500 nA
VPWRGD(OL) Power good output low IPWRGD(SINK) = 0mA to 2mA 1, 2, 3 250 300 mV
VINMIN_PWRGD Minimum VIN for valid PWRGD output Measured when VPWRGD ≤ 0.5V at 100μA 1, 2, 3 1 2 V
TSD(enter) Thermal shutdown enter temperature 170 °C
TSD(exit) Thermal shutdown exit temperature 135
TSD(HYS) Thermal shutdown hysteresis 35
(1) See the 5962R21221 SMD for additional information on the QML RHA devices and see the VID for additional information on the SEP devices.
(2) Subgroups are applicable for QML parts. For subgroup definitions, see the Quality Conformance Inspection table.
(3) VSENSE = (VSNS+) – (VSNS-)
(4) The device will not begin startup until the voltage on SS discharges below SSstartup in order to ensure proper soft start functionality.