SNVSAF7C August   2016  – October 2025 LM27762

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout
      2. 6.3.2 Input Current Limit
      3. 6.3.3 PFM Operation
      4. 6.3.4 Output Discharge
      5. 6.3.5 Power-Good Output (PGOOD)
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Enable Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Positive Low-Dropout Linear Regulator and OUT+ Voltage Setting
        2. 7.2.2.2 Charge-Pump Voltage Inverter
        3. 7.2.2.3 Negative Low-Dropout Linear Regulator and OUT– Voltage Setting
        4. 7.2.2.4 External Capacitor Selection
          1. 7.2.2.4.1 Charge-Pump Output Capacitor
          2. 7.2.2.4.2 Input Capacitor
          3. 7.2.2.4.3 Flying Capacitor
          4. 7.2.2.4.4 LDO Output Capacitor
        5. 7.2.2.5 Power Dissipation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.2 Enable Mode

Applying a voltage greater than 1.2 V to the EN+ pin enables the positive LDO. Applying a voltage greater than 1.2 V to the EN– pin enables the negative CP and LDO. When enabled, the positive and negative output voltages are equal to levels set by external resistors. Care must be taken to both the positive LDO and the inverting charge pump followed by negative LDO have enough headroom. Power Good ouput PGOOD indicates the status of OUT+ and OUT– voltage levels.