SNVSCE7D January   2024  – July 2025 TPS7H3014-SEP , TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.8 Typical Characteristics

RDLY_TMR = 10.5kΩ, RREG_TMR = 10.5kΩ, VPULL_UP1 = 3.3V, VPULL_UP2 = 3.3V, VFAULT = 10kΩ pull-up to VLDO, RHYS = 50kΩ, CREFCAP = 470nF, CVLDO = 1μF, CPULL_UP1 = 1μF, CPULL_UP2 = 1μF, unless otherwise noted.

TPS7H3014-SP TPS7H3014-SEP IQ_IN vs VIN Across Temperature in Waiting to Sequence UP State
VUP = VDOWN = 0V
Figure 6-1 IQ_IN vs VIN Across Temperature in Waiting to Sequence UP State
TPS7H3014-SP TPS7H3014-SEP IQ_IN vs VIN Across Temperature in Waiting to Sequence DOWN State
VUP = VDOWN = 3.3V
Figure 6-3 IQ_IN vs VIN Across Temperature in Waiting to Sequence DOWN State
TPS7H3014-SP TPS7H3014-SEP Undervoltage Lockout vs Temperature
RDLY_TMR = Floating VUP = VDOWN = 3.3V
RREG_TMR = 1.18MΩ
Figure 6-5 Undervoltage Lockout vs Temperature
TPS7H3014-SP TPS7H3014-SEP IHYS_SENSEx Current Distribution at Temperature of –55°C
VIN = 3V VSENSEx = 700mV
Figure 6-7 IHYS_SENSEx Current Distribution at Temperature of –55°C
TPS7H3014-SP TPS7H3014-SEP IHYS_SENSEx Current Distribution at Temperature of 125°C
VIN = 3V VSENSEx = 700mV
Figure 6-9 IHYS_SENSEx Current Distribution at Temperature of 125°C
TPS7H3014-SP TPS7H3014-SEP VTH_SENSEx Voltage Distribution at Temperature of +25°C
Figure 6-11 VTH_SENSEx Voltage Distribution at Temperature of +25°C
TPS7H3014-SP TPS7H3014-SEP REFCAP vs VIN Across Temperature
VUP = VDOWN = 0V
Figure 6-13 REFCAP vs VIN Across Temperature
TPS7H3014-SP TPS7H3014-SEP VLDO vs VIN Across Temperature
VUP = VDOWN = 0V
Figure 6-15 VLDO vs VIN Across Temperature
TPS7H3014-SP TPS7H3014-SEP VOL_EN1 vs Temperature Across VPULL_UP1 and VIN at ILOAD = –2mA
VUP = VDOWN = 0V ILOAD = –2mA
RREG_TMR = Floating
Figure 6-17 VOL_EN1 vs Temperature Across VPULL_UP1 and VIN at ILOAD = –2mA
TPS7H3014-SP TPS7H3014-SEP VOH_EN1 vs Temperature Across VPULL_UP1 at ILOAD = 2mA
VUP = VDOWN = 3.3V ILOAD = 2mA
RREG_TMR = Floating VIN = 12V
Figure 6-19 VOH_EN1 vs Temperature Across VPULL_UP1 at ILOAD = 2mA
TPS7H3014-SP TPS7H3014-SEP SREN1_RISE vs VPULL_UP1 Across Temperature
VUP = VDOWN = ↑ 3.3V VIN = 12V
RREG_TMR = Floating
Figure 6-21 SREN1_RISE vs VPULL_UP1 Across Temperature
TPS7H3014-SP TPS7H3014-SEP SRPWRGD_RISE vs VPULL_UP2 Across Temperature
VUP = VDOWN = ↑ 3.3V VIN = 12V
RREG_TMR = Floating
Figure 6-23 SRPWRGD_RISE vs VPULL_UP2 Across Temperature
TPS7H3014-SP TPS7H3014-SEP SREN1_FALL vs VPULL_UP1 Across Temperature
VUP = VDOWN = ↓ 0V VIN = 12V
RREG_TMR = Floating
Figure 6-25 SREN1_FALL vs VPULL_UP1 Across Temperature
TPS7H3014-SP TPS7H3014-SEP SRPWRGD_FALL vs VPULL_UP2 Across Temperature
VUP = VDOWN = ↓ 0V VIN = 12V
RREG_TMR = Floating
Figure 6-27 SRPWRGD_FALL vs VPULL_UP2 Across Temperature
TPS7H3014-SP TPS7H3014-SEP REN1_PULL_UP vs Temperature Across VPULL_UP1
VUP = VDOWN = 3.3V VIN = 12V
RREG_TMR = Floating ILOAD = 2mA
Figure 6-29 REN1_PULL_UP vs Temperature Across VPULL_UP1
TPS7H3014-SP TPS7H3014-SEP IQ_IN vs Temperature Across VIN in Waiting to Sequence UP State
VUP = VDOWN = 0V
Figure 6-2 IQ_IN vs Temperature Across VIN in Waiting to Sequence UP State
TPS7H3014-SP TPS7H3014-SEP IQ_IN vs Temperature Across VIN in Waiting to Sequence DOWN State
VUP = VDOWN = 3.3V
Figure 6-4 IQ_IN vs Temperature Across VIN in Waiting to Sequence DOWN State
TPS7H3014-SP TPS7H3014-SEP IHYS_SENSEx vs Temperature Across VIN and SENSEx Channel
VSENSEx = 700mV RREG_TMR = Floating
Figure 6-6 IHYS_SENSEx vs Temperature Across VIN and SENSEx Channel
TPS7H3014-SP TPS7H3014-SEP IHYS_SENSEx Current Distribution at Temperature of 25°C
VIN = 3V VSENSEx = 700mV
Figure 6-8 IHYS_SENSEx Current Distribution at Temperature of 25°C
TPS7H3014-SP TPS7H3014-SEP VTH_SENSEx Voltage Distribution at Temperature of –55°C
Figure 6-10 VTH_SENSEx Voltage Distribution at Temperature of –55°C
TPS7H3014-SP TPS7H3014-SEP VTH_SENSEx Voltage Distribution at Temperature of 125°C
Figure 6-12 VTH_SENSEx Voltage Distribution at Temperature of 125°C
TPS7H3014-SP TPS7H3014-SEP REFCAP vs Temperature Across VIN
VUP = VDOWN = 0V
Figure 6-14 REFCAP vs Temperature Across VIN
TPS7H3014-SP TPS7H3014-SEP VLDO vs Temperature Across VIN
VUP = VDOWN = 0V RREG_TMR = Floating
Figure 6-16 VLDO vs Temperature Across VIN
TPS7H3014-SP TPS7H3014-SEP VOL_EN1 vs Temperature Across VPULL_UP1 and VIN at ILOAD = –10mA
VUP = VDOWN = 0V ILOAD = –10mA
RREG_TMR = Floating
Figure 6-18 VOL_EN1 vs Temperature Across VPULL_UP1 and VIN at ILOAD = –10mA
TPS7H3014-SP TPS7H3014-SEP VOH_EN1 vs Temperature Across VPULL_UP1 at ILOAD = 10mA
VUP = VDOWN = 3.3V ILOAD = 10mA
RREG_TMR = Floating VIN = 12V
Figure 6-20 VOH_EN1 vs Temperature Across VPULL_UP1 at ILOAD = 10mA
TPS7H3014-SP TPS7H3014-SEP SREN1_RISE vs Temperature Across VPULL_UP1
VUP = VDOWN = ↑ 3.3V VIN = 12V
RREG_TMR = Floating
Figure 6-22 SREN1_RISE vs Temperature Across VPULL_UP1
TPS7H3014-SP TPS7H3014-SEP SRPWRGD_RISE vs Temperature Across VPULL_UP2
VUP = VDOWN = ↑ 3.3V VIN = 12V
RREG_TMR = Floating
Figure 6-24 SRPWRGD_RISE vs Temperature Across VPULL_UP2
TPS7H3014-SP TPS7H3014-SEP SREN1_FALL vs Temperature Across VPULL_UP1
VUP = VDOWN = ↓ 0V VIN = 12V
RREG_TMR = Floating
Figure 6-26 SREN1_FALL vs Temperature Across VPULL_UP1
TPS7H3014-SP TPS7H3014-SEP SRPWRGD_FALL vs Temperature Across VPULL_UP2
VUP = VDOWN = ↓ 0V VIN = 12V
RREG_TMR = Floating
Figure 6-28 SRPWRGD_FALL vs Temperature Across VPULL_UP2
TPS7H3014-SP TPS7H3014-SEP REN1_PULL_DOWN vs Temperature Across VPULL_UP1
VUP = VDOWN = 0V VIN = 12V
RREG_TMR = Floating ILOAD = –2mA
Figure 6-30 REN1_PULL_DOWN vs Temperature Across VPULL_UP1