SNVSCE7D January   2024  – July 2025 TPS7H3014-SEP , TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.1.3 Application Curves

TPS7H3014-SP TPS7H3014-SEP VIN vs Time During Sequence UP Figure 9-2 VIN vs Time During Sequence UP
TPS7H3014-SP TPS7H3014-SEP EN1 and VOUT1 vs Time During Sequence UP Figure 9-3 EN1 and VOUT1 vs Time During Sequence UP
TPS7H3014-SP TPS7H3014-SEP EN2 and VOUT2 vs Time During Sequence UP Figure 9-4 EN2 and VOUT2 vs Time During Sequence UP
TPS7H3014-SP TPS7H3014-SEP EN3 and VOUT3 vs Time During Sequence UP Figure 9-5 EN3 and VOUT3 vs Time During Sequence UP
TPS7H3014-SP TPS7H3014-SEP EN4 and VOUT4 vs Time During Sequence UP Figure 9-6 EN4 and VOUT4 vs Time During Sequence UP
TPS7H3014-SP TPS7H3014-SEP PWRGD and SEQ_DONE vs Time During Sequence UP Figure 9-7 PWRGD and SEQ_DONE vs Time During Sequence UP
TPS7H3014-SP TPS7H3014-SEP VIN vs Time During Sequence DOWN Figure 9-8 VIN vs Time During Sequence DOWN
TPS7H3014-SP TPS7H3014-SEP PWRGD and SEQ_DONE vs Time During Sequence DOWN Figure 9-9 PWRGD and SEQ_DONE vs Time During Sequence DOWN
TPS7H3014-SP TPS7H3014-SEP EN4 and VOUT4 vs Time During Sequence DOWN Figure 9-10 EN4 and VOUT4 vs Time During Sequence DOWN
TPS7H3014-SP TPS7H3014-SEP EN3 and VOUT3 vs Time During Sequence DOWN Figure 9-11 EN3 and VOUT3 vs Time During Sequence DOWN
TPS7H3014-SP TPS7H3014-SEP EN2 and VOUT2 vs Time During Sequence DOWN Figure 9-12 EN2 and VOUT2 vs Time During Sequence DOWN
TPS7H3014-SP TPS7H3014-SEP EN1 and VOUT1 vs Time During Sequence DOWN Figure 9-13 EN1 and VOUT1 vs Time During Sequence DOWN