SNVSCE7D January   2024  – July 2025 TPS7H3014-SEP , TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

HFT Package PW Package
22-Pin CFP 24-Pin TSSOP
Top View Top View
TPS7H3014-SP TPS7H3014-SEP TPS7H3014-SP TPS7H3014-SEP
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME HFT (22) NO. PW (24) NO.
SENSE1 1 1 I Non Inverting input of the comparator used to monitor the first rail to be sequenced up/down. Connect an external resistive divider between the rail to be monitored and GND with the middle point tied to the SENSE1, to set the VON and VOFF voltages. A voltage greater than 599mV (typ.) on this pin is considered as a regulated voltage rail (VON). The VOFF is set by the IHYS current and the top resistor from the resistive divider. Refer to Top and Bottom Resistive Divider Design Equations.
SENSE2 2 2 I Non Inverting input of the comparator used to monitor the second rail to be sequenced up/down. Connect an external resistive divider between the rail to be monitored and GND with the middle point tied to the SENSE2, to set the VON and VOFF voltages. A voltage greater than 599mV (typ.) on this pin is considered as a regulated voltage rail (VON). The VOFF is set by the IHYS current and the top resistor from the resistive divider. Refer to Top and Bottom Resistive Divider Design Equations.
SENSE3 3 3 I Non Inverting input of the comparator used to monitor the third rail to be sequenced up/down. Connect an external resistive divider between the rail to be monitored and GND with the middle point tied to the SENSE3, to set the VON and VOFF voltages. A voltage greater than 599mV (typ.) on this pin is considered as a regulated voltage rail (VON). The VOFF is set by the IHYS current and the top resistor from the resistive divider. Refer to Top and Bottom Resistive Divider Design Equations.
SENSE4 4 4 I Non Inverting input of the comparator used to monitor the fourth rail to be sequenced up/down. Connect an external resistive divider between the rail to be monitored and GND with the middle point tied to the SENSE4, to set the VON and VOFF voltages. A voltage greater than 599mV (typ.) on this pin is considered as a regulated voltage rail (VON). The VOFF is set by the IHYS current and the top resistor from the resistive divider. Refer to Top and Bottom Resistive Divider Design Equations.
REFCAP 5 5 O

1.2V internal reference. Requires a 470nF external capacitor to GND. Do not load this pin.

HYS 6 6 O Hysteresis. Connect a 50kΩ resistor between this pin and GND, to program the hysteresis current (typically 24μA) at SENSE1 to SENSE4. Is recommended using a resistor with 0.1% tolerance for accuracy purposes.
FAULT 7 7 O FAULT. Open drain output which is forced low by the state machine to indicate an internally generated fault. Is recommended to pull-up this pin to VLDO with a 10kΩ. However a different external voltage source can be used as the pull-up as long as is stable and does not change it value during the operation of the device.
UP 8 8 I Non inverting input of a comparator. A voltage greater than 599mV (typ.) will induce a rising edge and will start a sequence up. This pin can be driven by an external controller, or connected to a main rail trough an external resistive divider with the middle point connected to the UP pin to start the sequence up automatically. An fix hysteresis of 100mV (typ.) is present for noise stability.
IN 9 9 I

Input supply to the device. Input voltage range is from 3V to 14V. Connect at least a 0.1μF capacitor as close as possible to the pin.
REG_TMR 10 10 I/O Time to regulation timer. Connect a resistor to GND between 10.5kΩ and 1.18MΩ to set the allowed time for a SENSEx rail to reach the regulation threshold. The delay can be adjusted from 0.25ms to 25ms. Leave this pin floating when is desired to deactivate this feature.
DLY_TMR 11 11 I/O Delay timer. Connect a resistor to GND between 10.5kΩ and 1.18MΩ to set the sequence up and down delay. The delay can be adjusted from 0.25ms to 25ms. Leave this pin floating when no delay is needed on the system.
SEQ_DONE 12 14 O Sequence done. Push-Pull output with VOH level set by PULL_UP2 input supply voltage, that indicates when the sequence up or down is completed.
PWRGD 13 15 O Power Good. Push-Pull output with VOH level set by PULL_UP2, input input supply voltage, that indicates when all rails (SENSE1 to SENSE4) are in regulation.
GND 14 16 — Ground
VLDO 15 17 O

Output of internal regulator. Requires at least 1μF external capacitor to GND. Allowed loading of this regulator are: FAULT pull-up using a 10kΩ or to turn-off unused channels by connecting directly to SENSE2 to SENSE4 as needed.
DOWN 16 18 I Non inverting input of a comparator. A voltage lower than 498mV (typ.) will induce a falling edge and will start a sequence down. This pin can be driven by an external controller, or connected to a main rail trough an external resistive divider with the middle point connected to the DOWN pin to start the sequence down automatically. An fix hysteresis of 100mV (typ.) is present for noise stability.
PULL_UP2 17 19 I Input supply voltage to program the pull-up voltage for the push-pull output stage on SEQ_DONE and PWRGD. Connect at least a 1μF capacitor as close as possible to the pin.
PULL_UP1 18 20 I Input supply voltage to program the global pull-up voltage for the push-pull output stages on EN1 to EN4. Connect at least a 1μF capacitor as close as possible to the pin.
EN4 19 21 O Enable 4. Push pull output with VOH level set by the PULL_UP1 input supply voltage. Connect to the logical enable signal of the device to control and to be monitor by SENSE4.
EN3 20 22 O Enable 3. Push pull output with VOH level set by PULL_UP1 input supply voltage. Connect to the logical enable signal of the device to control and to be monitor by SENSE3.
EN2 21 23 O Enable 2. Push pull output with VOH level set by PULL_UP1 input supply voltage. Connect to the logical enable signal of the device to control and to be monitor by SENSE2.
EN1 22 24 O Enable 1. Push pull output with VOH level set by PULL_UP1 input supply voltage. Connect to the logical enable signal of the device to control and to be monitor by SENSE1.
NC — 12, 13 — No connect. This pin is not internally connected. It is recommended to connect these pins to GND to prevent charge buildup; however, these pins can also be left open or tied to any voltage between GND and VIN.
Thermal pad — — Internally grounded. It is recommended to connect this metal thermal pad to a large ground plane for effective heat dissipation.
Metal lid Lid — The lid is internally connected to the thermal pad and GND through the seal ring.
(1) I = Input, O = Output, I/O = Input or Output, — = Other