SNVU896A February   2025  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Jumpers
      2. 2.1.2 EVM Test Points
    2. 2.2 EVM Setup and Operation
      1. 2.2.1  Input Supply Voltage (VDD)
      2. 2.2.2  SENSE
      3. 2.2.3  VSENSE
      4. 2.2.4  OUT OV
      5. 2.2.5  OUT UV
      6. 2.2.6  LOW UV
      7. 2.2.7  ADJ OV
      8. 2.2.8  ADJ UV
      9. 2.2.9  BIST EN
      10. 2.2.10 Reset Time Delay (CTR)
      11. 2.2.11 Sense Time Delay (CTS)
  7. 3Implementation Results
    1. 3.1 EVM Performance Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Revision History

2.2.3 VSENSE

The VSENSE is connected through VSENSE on the board. The VSENSE voltage is a scale down SENSE voltage as seen in the equation below:

Equation 1. V S E N S E   = S E N S E V S E N S E   S c a l i n g

The VSENSE has an integrated 10Mhz buffer and can be directly connected to an ADC.