SNVU896A February   2025  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Jumpers
      2. 2.1.2 EVM Test Points
    2. 2.2 EVM Setup and Operation
      1. 2.2.1  Input Supply Voltage (VDD)
      2. 2.2.2  SENSE
      3. 2.2.3  VSENSE
      4. 2.2.4  OUT OV
      5. 2.2.5  OUT UV
      6. 2.2.6  LOW UV
      7. 2.2.7  ADJ OV
      8. 2.2.8  ADJ UV
      9. 2.2.9  BIST EN
      10. 2.2.10 Reset Time Delay (CTR)
      11. 2.2.11 Sense Time Delay (CTS)
  7. 3Implementation Results
    1. 3.1 EVM Performance Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Revision History

PCB Layout

Figure 4-2 and Figure 4-3 show the top and bottom assemblies of the printed circuit board (PCB) to display the component placement of the EVM.

Figure 4-4 and Figure 4-5 show the top and bottom layouts, Figure 4-6 and Figure 4-7 show the top and bottom layers, and Figure 4-8 shows the top solder mask of the EVM.

TPS371KEVM Component Placement - Top AssemblyFigure 4-2 Component Placement - Top Assembly
TPS371KEVM Layout - TopFigure 4-4 Layout - Top
TPS371KEVM Top LayerFigure 4-6 Top Layer
TPS371KEVM Top Solder MaskFigure 4-8 Top Solder Mask
TPS371KEVM Component Placement - Bottom AssemblyFigure 4-3 Component Placement - Bottom Assembly
TPS371KEVM Layout - BottomFigure 4-5 Layout - Bottom
TPS371KEVM Bottom LayerFigure 4-7 Bottom Layer