SPRABA5D January   2014  – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810

 

  1.   Using the AM18xx Bootloader
    1.     Trademarks
    2. 1  Introduction
    3. 2  Boot Modes
    4. 3  Non-AIS Boot Modes
      1. 3.1 NOR Boot
        1. 3.1.1 Legacy NOR Boot
        2. 3.1.2 Direct NOR Boot
        3. 3.1.3 AIS NOR Boot
      2. 3.2 Host Port Interface (HPI) Boot
      3. 3.3 Emulation Debug Boot
    5. 4  Application Image Script (AIS) Boot
      1. 4.1  Section Load Command (0x58535901)
      2. 4.2  Section Fill Command (0x5853590A)
      3. 4.3  Enable CRC Command (0x58535903)
      4. 4.4  Disable CRC Command (0x58535904)
      5. 4.5  Validate CRC Command (0x58535902)
      6. 4.6  Jump & Close Command (0x58535906)
      7. 4.7  Jump Command (0x58535905)
      8. 4.8  Sequential Read Enable Command (0x58535963)
      9. 4.9  Function Execute Command (0x5853590D)
      10. 4.10 Boot Table Command (0x58535907)
    6. 5  AISgen: Tool to Generate Boot Script (AIS Image)
      1. 5.1 Installation
      2. 5.2 Getting Started
      3. 5.3 Generating AIS
        1. 5.3.1  Boot Mode and Boot Peripheral Setup
        2. 5.3.2  Phase-Locked Loop (PLL) Setup
        3. 5.3.3  Synchronous Dynamic Random Access Memory (SDRAM) Setup
        4. 5.3.4  DDR Setup
        5. 5.3.5  PSC Setup
        6. 5.3.6  Pin Multiplexing Setup
        7. 5.3.7  Application File Selection
        8. 5.3.8  AIS File Selection
        9. 5.3.9  Status and Messages
        10. 5.3.10 Additional AIS Options
          1. 5.3.10.1 CRC
          2. 5.3.10.2 Specifying the Application Entrypoint
        11. 5.3.11 Command Line Usage
    7. 6  Master Boot – Booting From a Slave Memory Device
      1. 6.1 I2C EEPROM Boot
      2. 6.2 SPI EEPROM or Flash Boot
      3. 6.3 NOR Flash Boot
      4. 6.4 NAND Flash Boot
      5. 6.5 MMC/SD Boot
    8. 7  Slave Boot – Booting From an External Master Host
      1. 7.1 About the AIS Interpreter on the Host
      2. 7.2 Start-Word Synchronization (SWS)
      3. 7.3 Ping Op-Code Synchronization (POS)
      4. 7.4 Opcode Synchronization (OS)
    9. 8  UART Boot Host - Using Your PC as a UART Boot Master
      1. 8.1 Getting Started
      2. 8.2 Booting the Device
      3. 8.3 The AIS_Util.cs Source Code
    10. 9  Boot Requirements, Constraints and Default Settings
      1. 9.1 General Comments
      2. 9.2 UART-Boot Modes
      3. 9.3 I2C-Boot Modes
      4. 9.4 SPI-Boot Modes
      5. 9.5 NOR-Boot Modes
      6. 9.6 NAND-Boot Modes
      7. 9.7 MMC/SD-Boot Modes
      8. 9.8 HPI-Boot Modes
    11. 10 References
  2.   A Boot Mode Selection Table
    1.     A.1 Boot Mode Selection Table
  3.   B Details of Supported NAND Devices
    1.     B.1 Details of Supported NAND Devices
  4.   C CRC Computation Algorithm
    1.     C.1 CRC Computation Algorithm
  5.   D Details of Pre-Defined ROM Functions
    1.     D.1 PLL0 Configuration (Index = 0, Argument Count = 2)
    2.     D.2 PLL1 Configuration (Index = 1, Argument Count = 2)
    3.     D.3 Clock Configuration (Index = 2, Argument Count = 1)
      1.      D.3.1 SPI Master Register
      2.      D.3.2 I2C Master Register
      3.      D.3.3 UART Slave Register
      4.      D.3.4 MMC/SD Register
    4.     D.4 mDDR/DDR2 Controller Configuration (Index = 3, Argument Count = 8)
    5.     D.5 EMIFA SDRAM Configuration (Index = 4, Argument Count = 5)
    6.     D.6 EMIFA Async Configuration (Index = 5, Argument Count = 5)
    7.     D.7 PLL and Clock Configuration (Index = 6, Argument Count = 3)
    8.     D.8 Power and Sleep Configuration (PSC) (Index = 7, Argument Count = 1)
    9.     D.9 Pinmux Configuration (Index = 8, Argument Count = 3)
  6.   E ROM Revision History
    1.     E.1 ROMID: D800K002, Silicon Revision 1.0
    2.     E.2 ROMID: D800K004, Silicon Revision 1.1
    3.     E.3 ROMID: D800K006, Silicon Revision 2.0
    4.     E.4 ROMID: D800K008, Silicon Revision 2.1
  7.   Revision History

D.3.2 I2C Master Register

The I2C master register is shown in Figure 32 and described in Table 20.

Figure 32. I2C Master Register
31 24 23 16 15 8 7 0
Arg1 Reserved IPSC ICCL ICCH

Table 20. I2C Master Register Field Descriptions

Bit Field Value Description
31-24 Reserved 0 Reserved
23-16 IPSC Value to be programmed to I2C ICPSC register
15-8 ICCL Value to be programmed to I2C ICCLKL register
7-0 ICCH Value to be programmed to I2C ICCLKH register