SPRABA5D January 2014 – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810
The UART master register is shown in Figure 33 and described in Table 21.
31 | 24 | 23 | 16 | 15 | 8 | 7 | 0 |
Arg1 | Reserved | OSR | DLH | DLL |
Bit | Field | Value | Description |
---|---|---|---|
31-24 | Reserved | 0 | Reserved |
23-16 | OSR | Value to be programmed to OSR field of UART MDR register | |
15-8 | DLH | Value to be programmed to UART DLH register | |
7-0 | DLL | Value to be programmed to UART DLL register |