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Product details

Parameters

Arm MHz (Max.) 375, 456 DRAM DDR2, LPDDR Arm CPU Arm9 USB 1 SPI 2 I2C 2 Display type 1 LCD Operating temperature range (C) -40 to 105, -40 to 90, 0 to 90 Serial I/O McASP, McBSP, SPI, I2C, UART, SATA UART 3 open-in-new Find other Other Sitara processors

Package | Pins | Size

NFBGA (ZCE) 361 169 mm² 13 x 13 NFBGA (ZWT) 361 256 mm² 16 x 16 open-in-new Find other Other Sitara processors

Features

  • 375- and 456-MHz ARM926EJ-S RISC MPU
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
      • Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Transmit and Receive Clocks
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
  • 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Commercial or Extended Temperature
open-in-new Find other Other Sitara processors

Description

The AM1806 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The universal parallel port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) is included providing a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet AM1806 ARM Microprocessor datasheet (Rev. F) Mar. 21, 2014
* Errata AM1806 ARM Microprocessor Silicon Errata (Revs 2.3, 2.1 and 2.0) (Rev. H) Sep. 17, 2014
Technical articles How to affordably add EtherNet/IP, EtherCAT and PROFINET to an autonomous factory Aug. 24, 2020
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun. 01, 2020
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Y) Feb. 04, 2020
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. V) Feb. 04, 2020
Application note Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x Dec. 20, 2019
Technical articles Designing smarter remote terminal units for microgrids Oct. 02, 2019
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) Jun. 03, 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) Jun. 03, 2019
Technical articles Security versus functional safety: a view from the Processor Software Development Kit May 31, 2019
Application note Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx Apr. 25, 2019
Application note General Hardware Design/BGA PCB Design/BGA Feb. 22, 2019
Application note OMAP-L13x / C674x / AM1x schematic review guidelines Feb. 14, 2019
Application note Using the AM18xx Bootloader (Rev. D) Jan. 22, 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) Nov. 19, 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) Nov. 19, 2018
Application note High-Speed Interface Layout Guidelines (Rev. H) Oct. 11, 2018
Technical articles Simplified software development through the Processor SDK and tools Oct. 02, 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS Sep. 24, 2018
User guide PRU Assembly Instruction User Guide Feb. 16, 2018
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. U) Feb. 07, 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) Jan. 16, 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) Jan. 16, 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) Sep. 30, 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) Sep. 30, 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) Jun. 21, 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) Jun. 21, 2017
User guide AM1806 ARM Microprocessor Technical Reference Manual (Rev. C) Sep. 12, 2016
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) Apr. 30, 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) Apr. 30, 2016
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) Nov. 05, 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) Nov. 05, 2014
Application note AM18xx Pin Multiplexing Utility (Rev. A) Dec. 06, 2011
Application note Powering the AM1806, AM1808, and AM1810 with the TPS650061 Sep. 06, 2011
Application note High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS (Rev. C) Aug. 29, 2011
Application note Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO (Rev. B) Aug. 29, 2011
Application note Powering OMAP-L132/L138, C6742/4/6, and AM18x with TPS65070 (Rev. B) Aug. 29, 2011
Application note Simple Power Solution Using LDOs (Rev. B) Aug. 29, 2011
Application note AM18x power consumption summary Aug. 30, 2010
Application note High-Efficiency Power Solution Using DC/DC Converters With DVFS (Rev. A) May 05, 2010
Application note High-Integration, High-Efficiency Power Solution Using DC/DC Converters w/DVFS (Rev. A) May 05, 2010
Application note TMS320C6748/46/42 & OMAP-L132/L138 USB Downstream Host Compliance Testing Aug. 17, 2009
Application note TMS320C6748/46/42 & OMAP-L1x8 USB Upstream Device Compliance Testing Aug. 17, 2009
Application note TMS320C674x/OMAP-L1x USB Compliance Checklist Mar. 12, 2009
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) Jul. 17, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

DEBUG PROBE Download
XDS200 USB Debug Probe
TMDSEMU200-U
295
Description

The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)

Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBE Download
995
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBE Download
1495
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Software development

SOFTWARE DEVELOPMENT KIT (SDK) Download
Linux EZ Software Development Kit (EZSDK) for Sitara™ Processors
LINUXEZSDK-SITARA SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

Features

The Sitara Linux SDK features:

  • Open Linux support
  • GUI-based application launcher
  • 3-D graphics support
  • Example application with available source code

The Linux SDK includes the following components:

  • Linux kernel and Bootloaders
  • File system
  • Qt/Webkit application framework
  • Application launcher
  • 3D graphics (...)
SOFTWARE DEVELOPMENT KIT (SDK) Download
Programmable Real-time Unit (PRU) Software Support Package
PRU-SWPKG The PRU Software Support Package is an add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit sub-system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors.  The PRU-ICSS achieves deterministic, real-time (...)
SOFTWARE DEVELOPMENT KIT (SDK) Download
Windows® Embedded Compact/CE SDK - ARM9™-based AM18x, OMAP-L13x Processor
WINCESDK-AM1XOMAPL1X Microsoft Windows Embedded Compact (WEC7) and CE (WinCE 6.0) operating systems are optimized for embedded devices that require minimum storage based on a componentized architecture.

WinCE BSPs for ARM9-based processors are now available from Adeneo Embedded.

DRIVER OR LIBRARY Download
StarterWare for ARM® based TI Sitara Processors
STARTERWARE-SITARA StarterWare provides C-based no-OS platform support for TI's ARM9™ and ARM® Cortex™ A8 based devices. StarterWare provides device abstraction layer libraries, peripheral programming examples such as Ethernet, graphics and USB, and board level example applications. StarterWare can be (...)
Features
  • Peripheral programming interface
  • Example applications for each peripheral to demonstrate programming and usage of the peripheral
  • Software portability across devices for a given peripheral
  • Tool-chain agnostic C code (Some startup code will be in assembly and hence some part of the code will be tool (...)
IDE, CONFIGURATION, COMPILER OR DEBUGGER Download
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM Processors
CCSTUDIO-SITARA

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

OPERATING SYSTEM (OS) Download
Mentor Graphics Nucleus RTOS
Provided by Mentor Graphics Corporation — Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify application (...)

Design tools & simulation

SIMULATION MODEL Download
SPRM482.ZIP (8 KB) - BSDL Model
SIMULATION MODEL Download
SPRM483A.ZIP (120 KB) - IBIS Model
SIMULATION MODEL Download
SPRM484.ZIP (8 KB) - BSDL Model
SIMULATION MODEL Download
SPRM485A.ZIP (121 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
NFBGA (ZCE) 361 View options
NFBGA (ZWT) 361 View options

Ordering & quality

Support & training

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