SPRACK2A September   2019  – March 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

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3.5.2.1 Bootrom Features

For specific bootrom features on F28004x and F28002x for hardware or software consideration, see Table 9.

Table 9. Bootrom Comparison Table

F28004x F28002x
System Debug (ERAD) NMI is disabled NMI is enabled.  Bootrom exception handler is updated for this NMI
HWBIST HWBIST is not available HWBIST is available
CPU Boot Mode GPIO Assignments On 64-pin package, F28004x and F28002x have similar options however the BOOTDEFx values are different.  For boot mode GPIO assignment on the other pin package types, see the Bootrom section in the device-specific data sheet.
BMSP Restrictions - Do not use pins GPIO20-33, GPIO36, GPIO38 and GPIO60-233 GPIO20, GPIO21,GPIO36,GPIO38,GPIO47-60 and GPIO63-223
RAM Initialization RAM initialization occurs on POR and XRS RAM initialization occurs only on POR
ROM Table ROM tables for F28004x and F28002x are different. For details, see the device-specific TRM.
PBIST(MPOST) Status Flag Flag is reset for every reset type Flag is reset only for POR reset type
PBIST(MPOST) Execution Speed Will execute either at maximum SYSCLK speed or INTOSC clock Will execute either at maximum SYSCLK or half of maximum SYSCLK speed