SPRACU5C June 2021 – September 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
PRU_ICSSG pins can be multiplexed at the processor level using the PADCONFIGx registers and also at the PRU_ICSSG IP level. Take care of the schematic connections for the required interface, in particular review the differences between the RGMII connections and the MII connections for the transmit pins including the clock.
Some industrial protocols require the use of 10/100-Mbit EPHY using the MII interface. Verify with the EPHY manufacturer (as required) to determine if the MII interface required by the industrial protocol is supported.