SPRADN2 January   2025 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3519 , MSPM0L1227 , MSPM0L1228 , MSPM0L2227 , MSPM0L2228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Nonvolatile Memory (NVM) Basic Introduction
    1. 1.1 Flash Memory Protection
  5. 2Customer Secure Code (CSC) Introduction
    1. 2.1 CSC Execution Overview
    2. 2.2 CSC Memory Maps
    3. 2.3 CSC Execution Process
  6. 3Bank Swap Example Implementation
    1. 3.1 CSC Code Project Preparation
      1. 3.1.1 Enable CSC in NONMAIN
      2. 3.1.2 Implementation of CSC Application Code - Bank Swap Feature
    2. 3.2 Application Code Project Preparation
  7. 4Common Use Case Introduction
  8. 5Data Bank Introduction
    1. 5.1 Data Bank Protection
    2. 5.2 Data Bank Erase Write Operation
  9. 6Summary
  10. 7References

1.1 Flash Memory Protection

To meet diverse security requirements, various types of flash memory protection mechanisms are provided.

Table 1-3 Memory Protection Mechanisms on MSPM0 Dual Bank Devices
Memory Protection Description
Bank Swapping In dual-bank or quad-bank devices, based on which bank (or pair) is executable, that bank (pair) gets readexecute privileges and loses write or erase privileges. The other bank (or pair) is readable, and writeable but not executable. This mechanism enforces the policy that any firmware update can only be saved in the writeable bank in the current session but can never be executed.
Write Protection
  1. Write-protection that is enforced by TI boot-code (NONMAIN configuration).
  2. Write-protection that is enforced by CSC to further protect data that is allowed to update but that must not be modified by the application.
  3. Write-protection in the context of bank swap (covered in Section 3).
Read-Execute Protection A region of flash memory can be configured for read-execute protection; read and instruction fetch accesses to this region returns an error. CPU, DMA and debugger accesses are all treated the same way.
IP Protection A region of flash memory can be configured for read protection; read accesses to this region returns an error while instruction fetch accesses are allowed. CPU, DMA and debugger accesses are all treated the same way.
Data Bank Protection A region of flash DATA bank can be configured for read-write protection - either reads or writes or both types of accesses can be blocked. CPU, DMA and debugger accesses are all treated the same way.
Note: Please find detailed operation description for each flash protection method in TRM chapter Security.