SPRADN2 January   2025 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3519 , MSPM0L1227 , MSPM0L1228 , MSPM0L2227 , MSPM0L2228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Nonvolatile Memory (NVM) Basic Introduction
    1. 1.1 Flash Memory Protection
  5. 2Customer Secure Code (CSC) Introduction
    1. 2.1 CSC Execution Overview
    2. 2.2 CSC Memory Maps
    3. 2.3 CSC Execution Process
  6. 3Bank Swap Example Implementation
    1. 3.1 CSC Code Project Preparation
      1. 3.1.1 Enable CSC in NONMAIN
      2. 3.1.2 Implementation of CSC Application Code - Bank Swap Feature
    2. 3.2 Application Code Project Preparation
  7. 4Common Use Case Introduction
  8. 5Data Bank Introduction
    1. 5.1 Data Bank Protection
    2. 5.2 Data Bank Erase Write Operation
  9. 6Summary
  10. 7References

4 Common Use Case Introduction

The dual bank memory can be configured and used as a single large NVM block with continuous addressing (with few exceptions, not covered in this document). There are significant advantages when the NVM is configured to serve as two parallel blocks, the most important is the possibility to write on one bank without interrupting reading (and fetching instructions) from the other bank. This is the most important prerequisite to perform the updates without breaking the execution of the code from the program NVM.

When designing an application that uses a dual bank device, there are several choices to make on how to utilize the second half of the program memory.

Also referred to as live field upgrade, this is a process that allows the user to modify the code and configuration without disturbing the normal operation of the device. There are more advantages compared to the simple boot loader design:

  • Boot loader code back up: Boot code can be updated when using the dual bank
  • Application code back up: The original application code is still functional if the boot loading fails
  • EEPROM emulation: An application can execute code out of one flash bank while a second flash bank is used for writing data without stalling the application execution

Table 4-1 compares the differences between single bank and multi bank devices related to flash operations (Erase and Program).

Table 4-1 Flash Operation Differences on Same Bank and Different Bank
On Same Bank On Different Bank
Flash Operation (Erase and Program) Flash operation command executed in SRAM. When operates on the same bank of application code. Same as Single Bank device.
When operates on the different bank of application code. Flash operation command executed in flash.
Interrupts during flash operation (Erase and Program) TI recommends to disable interrupts or move important interrupt routine into SRAM before flash operation. Since an ongoing program or erase operation stalls all read requests to the flash memory until the operation has completed and the flash controller has released control of the bank. When operates on the same bank of application code. Same as Single Bank device.
When operates on the different bank of application code. Interrupts are responded to on time.