SPRADN2 January   2025 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3519 , MSPM0L1227 , MSPM0L1228 , MSPM0L2227 , MSPM0L2228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Nonvolatile Memory (NVM) Basic Introduction
    1. 1.1 Flash Memory Protection
  5. 2Customer Secure Code (CSC) Introduction
    1. 2.1 CSC Execution Overview
    2. 2.2 CSC Memory Maps
    3. 2.3 CSC Execution Process
  6. 3Bank Swap Example Implementation
    1. 3.1 CSC Code Project Preparation
      1. 3.1.1 Enable CSC in NONMAIN
      2. 3.1.2 Implementation of CSC Application Code - Bank Swap Feature
    2. 3.2 Application Code Project Preparation
  7. 4Common Use Case Introduction
  8. 5Data Bank Introduction
    1. 5.1 Data Bank Protection
    2. 5.2 Data Bank Erase Write Operation
  9. 6Summary
  10. 7References

3.2 Application Code Project Preparation

The only need to do here is to arrange the flash memory in the linker file. This is required to avoid address overlap with the application code and CSC code in the same bank. Please note that application code on both banks must also start at the same address due to the CSC code policy. An example how to configure the linker file for the application code is provided below. 

-uinterruptVectors
--stack_size=256
--define=_CSC_SIZE_=(6*1024)

/* Note: SRAM is partitioned into two separate sections SRAM_BANK0 and SRAM_BANK1
 * to account for SRAM_BANK1 being wiped out upon the device entering any low-power
 * mode stronger than SLEEP. Thus, this is up to the end-user to enable SRAM_BANK1 for
 * applications where the memory is considered lost outside of RUN and SLEEP Modes.
 */

MEMORY
{
    FLASH_APP       (RX)  : origin = _CSC_SIZE_, length = (0x00040000 - _CSC_SIZE_)
    SRAM_BANK0      (RWX) : origin = 0x20200000, length = 0x00010000
    SRAM_BANK1      (RWX) : origin = 0x20210000, length = 0x00010000
    DATA            (R)   : origin = 0x41D00000, length = 0x00004000
}

SECTIONS
{
    .intvecs:   > _CSC_SIZE_
    .text   : palign(8) {} > FLASH_APP
    .const  : palign(8) {} > FLASH_APP
    .cinit  : palign(8) {} > FLASH_APP
    .pinit  : palign(8) {} > FLASH_APP
    .rodata : palign(8) {} > FLASH_APP
    .ARM.exidx    : palign(8) {} > FLASH_APP
    .init_array   : palign(8) {} > FLASH_APP
    .binit        : palign(8) {} > FLASH_APP
    .TI.ramfunc   : load = FLASH_APP, palign(8), run=SRAM_BANK0, table(BINIT)

    .vtable :   > SRAM_BANK0
    .args   :   > SRAM_BANK0
    .data   :   > SRAM_BANK0
    .bss    :   > SRAM_BANK0
    .sysmem :   > SRAM_BANK0
    .TrimTable :  > SRAM_BANK0
    .stack  :   > SRAM_BANK0 (HIGH)

    .DataBank   : {} > DATA
}

Customers can add other functions in the application code project according to the project requirements. When the application code project is ready for programming, remember to change the erase method in the IDE or programmer since the application project does not include NONMAIN configuration. TI recommends to use Erase MAIN memory only.

Erase Main Memory Only Figure 3-3 Erase Main Memory Only