SPRADS3 July   2025 AM62P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 DSS Components
    2. 1.2 PLL and Output Routing with DSS
  5. 2Configuring Individual Displays
    1. 2.1 Configuring OLDI
    2. 2.2 Configuring DPI
    3. 2.3 Configuring DSI
  6. 3Configuring Simultaneous Displays
  7. 4Software Configuration
    1. 4.1 OLDI (Dual Link)
    2. 4.2 OLDI (Single Link - Cloned Mode)
    3. 4.3 OLDI (Single Link - Independent Mode)
    4. 4.4 DPI / HDMI
    5. 4.5 DSI
  8. 5Summary
  9. 6References

2.3 Configuring DSI

There are 2 possible ways of driving DSI controlled by Mux 240

  1. Using PLL 18 at maximum 300MHz pixel clock.
  2. Using PLL 17 at maximum 165MHz pixel clock.
Display Interface DSS VP Config PLL Config Maximum Pixel Frequency Mux Summary
DSS0 VP0 DSS0 VP1 DSS1 VP0 DSS1 VP1 PLL 16 PLL 17 PLL 18
DSI 300MHz N/A
165MHz Mux 240 Mux 240: Select 1 -> PLL 17. For more information, see CFG0_DSS1_DISPC0_CLKSEL(bit18)