SPRADS3 July   2025 AM62P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 DSS Components
    2. 1.2 PLL and Output Routing with DSS
  5. 2Configuring Individual Displays
    1. 2.1 Configuring OLDI
    2. 2.2 Configuring DPI
    3. 2.3 Configuring DSI
  6. 3Configuring Simultaneous Displays
  7. 4Software Configuration
    1. 4.1 OLDI (Dual Link)
    2. 4.2 OLDI (Single Link - Cloned Mode)
    3. 4.3 OLDI (Single Link - Independent Mode)
    4. 4.4 DPI / HDMI
    5. 4.5 DSI
  8. 5Summary
  9. 6References

1.1 DSS Components

Figure 1-1 shows the flow diagram of data within the DSS. Table 1-1 gives a brief overview for each of the components inside DSS.

DISPC Architecture Overview Figure 1-1 DISPC Architecture Overview
Table 1-1 DSS Components Overview
Component Name Description Supported Features
DMA Engine Allows direct access to the frame buffer located inside the device system memory. Multiple DMA Internal Buffers: 2 DMA buffers and each supports size of 40 KB
1D transfers only
Self refresh mode: Data is fetched once into the DMA buffer and then the following frames re-use the DMA channels to display on the screen.
Video Pipeline (VID) / Video Lite Pipeline (VIDL)

DSS has 2 pipelines: Video pipeline and Video-lite pipeline. These pipelines are the frame processing entity of the DSS. They carry out operations directly on the frames fetched by the DMA Engine.

 Supports all Pixel Formats
All the BITMAP, YUV and RGB pixel formats are supported.
Color Space Conversion
Converts pixels from YUV color-space to RGB color-space.
Video Color Look-Up Table
  • Convert BITMAP pixels to RGB
  • Inverse gamma correction

Scaler Polyphase Filters*
  • Up-sample or Down-sample the pixels
  • Anti-aliasing Reduction
  • Chrominance Resampling

Luma Key
Make pixels whose luminance falls under a certain range transparent.
The video-lite pipeline does not have scaler filters, but has dedicated Chrominance Upsamplers.
Overlay (OVL) Manager

Compositing selected input layers together to generate the final display output frame.
Note: OVL Managers only accepts RGB formats for inputs and outputs in RGB formats.
Programmable Background Color
DSS is capable of writing a solid color in the background image.
Composition
Composite multiple layers (VID and/or VIDL) on top of the background color
Transparency Color Key
Source color transparency: Top layer pixel that meets the source transparency color check is made transparent.
Destination color transparency: Top layer pixel is made transparent, only if the bottom layer pixel does not meet the destination transparency color check.
Alpha Blending
Global alpha and per pixel alpha modes supported.
Z ordering
Determines the order in which the selected layers are blended.
Color Bar Test
Ability to generate a color bar pattern for testing.
Video Port (VP)

Receives the final frame as input from Overlay Managers and generates video signals

 Output Format
  • RGB
    • RGB-444/565/666/888
  • YUV
    • BT.1120 and BT.656 Modes

Color Space Conversion / Color Phase Rotation
  • Converts pixels from RGB color-space to YUV color-space.
  • Change the phases of the RGB output to either GBR or BRG.

Temporal Dithering
Minimizes the color banding when displaying the data on an LCD panel with color-depth lower than 24-bits.
Multiple Cycle Output Format (using TDM)
Pixels are transmitted on a lesser number of video-output lines in 1 to 3 cycles.
Safety For safety critical system applications, DSS supports various safety features in hardware. Data correctness check
To verify intended data is shown correctly on the display.
Freeze frame detection
To notify a possible frame freeze, when there is no change in the display frame over multiple frame periods.

Table 1-1 lists a high level overview of the various features. For more details, see the DSS chapter in the TRM.