SPRADS3 July   2025 AM62P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 DSS Components
    2. 1.2 PLL and Output Routing with DSS
  5. 2Configuring Individual Displays
    1. 2.1 Configuring OLDI
    2. 2.2 Configuring DPI
    3. 2.3 Configuring DSI
  6. 3Configuring Simultaneous Displays
  7. 4Software Configuration
    1. 4.1 OLDI (Dual Link)
    2. 4.2 OLDI (Single Link - Cloned Mode)
    3. 4.3 OLDI (Single Link - Independent Mode)
    4. 4.4 DPI / HDMI
    5. 4.5 DSI
  8. 5Summary
  9. 6References

2.2 Configuring DPI

There are three possible ways of driving DPI and all operating at maximum 165MHx pixel clock using multiple mux configurations.

  1. Using DSS0 VP1
  2. Using DSS1 VP0
  3. Using DSS1 VP1

For more information, please see CFG0_DPI0_OUT_SEL.

Table 2-2 DPI Configurations
Display Interface DSS VP Config PLL Config Max. Pixel Frequency Mux Summary
DSS0 VP0 DSS0 VP1 DSS1 VP0 DSS1 VP1 PLL 16 PLL 17 PLL 18
DPI 165MHz N/A
165MHz Mux 241and Mux 245 Mux 241: Select 1 -> PLL17 For more information, please refer to: CFG0_DSS1_DISPC0_CLKSEL(bit16) Mux 245: Select 1 -> DSS1 VP0 For more information, see CFG0_DPI0_OUT_SEL
165MHz Mux 240 and Mux 245 Mux 240: Select 1 -> PLL17 For more information, please refer to: CFG0_DSS1_DISPC0_CLKSEL (BIT18)
Mux 245: Select 2-> DSS1 VP1 For more information, see: CFG0_DPI0_OUT_SEL