SPRADS3 July   2025 AM62P

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 DSS Components
    2. 1.2 PLL and Output Routing with DSS
  5. 2Configuring Individual Displays
    1. 2.1 Configuring OLDI
    2. 2.2 Configuring DPI
    3. 2.3 Configuring DSI
  6. 3Configuring Simultaneous Displays
  7. 4Software Configuration
    1. 4.1 OLDI (Dual Link)
    2. 4.2 OLDI (Single Link - Cloned Mode)
    3. 4.3 OLDI (Single Link - Independent Mode)
    4. 4.4 DPI / HDMI
    5. 4.5 DSI
  8. 5Summary
  9. 6References

2.1 Configuring OLDI

There are five possible ways of driving OLDI and the OLDI is controlled by Mux 235.

  1. Single-Link OLDI controlled by DSS0 VP0 operating at maximum 165MHz pixel clock.
  2. Single-Link OLDI controlled by DSS1 VP0 operating at maximum 100MHz pixel clock.
  3. Two independent single-link OLDI, one controlled by DSS0 VP0 operating at maximum 165MHz pixel clock and other controlled by DSS1 VP0 operating at maximum. 100MHz pixel clock.
  4. Two cloned single-link OLDI, both controlled by DSS0 VP0 operating at maximum 165MHz pixel clock.
  5. Dual-link OLDI controlled by DSS0 VP0 operating at maximum 300MHz pixel clock.
Table 2-1 OLDI Configurations
Display InterfaceDSS VP ConfigPLL ConfigMax. Pixel FrequencyMUXSummary
DSS0 VP0DSS0 VP1DSS1 VP0DSS1 VP1PLL16PLL17PLL18
OLDI(SL) [OLDI TX0] 165MHzN/A
OLDI(SL) [OLDI TX1] 100MHzMux 235Mux 235 controls the OLDI1 Input and PLL Clock. Value of 0 means DSS0 VP0 + PLL16 and Value of 1 means DSS1 VP0 + PLL 18. For more information, see CFG0_OLDI1_CLKSEL in the TRM
2x OLDI(SL) [OLDI TX0 & OLDI TX1] 165MHZ and 100MHZMux 235Mux 235 controls the OLDI1 Input and PLL Clock. Value of 0 means DSS0 VP0 + PLL16 and Value of 1 means DSS1 VP0 + PLL 18. For more information, see the CFG0_OLDI1_CLKSEL in TRM
Clone Mode [OLDI TX0 and OLDI TX1] 165MHzN/ADo not need to configure other DSS and drives the DSS
OLDI(DL) [OLDI TX0 and OLDI TX1] 300MHzN/A