SPRADT4 July   2025 TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   Abstract
  3. 1Introduction and Functional Block Diagram of TMS320F2838xD
  4. 2Limitations of Data Transfer Between CPU2 and CPU1.CLA1 via the IPC Module
  5. 3Principle of Data Transfer Between CPU2 and CPU1.CLA1 Using "IO Trigger + DMA Transfer"
  6. 4Verification of the "IO Trigger + DMA Transfer" Method
    1. 4.1 Timing Description and Code Implementation
    2. 4.2 Experimental Setup
    3. 4.3 Timing Waveform Verification
  7. 5Summary
  8. 6References

4.2 Experimental Setup

Based on the aforementioned experimental design, verification was performed using TI's development boards: TMDSCNCD28388D and TMDSHSECDOCK.

Test Equipment:

  1. TMDSCNCD28388D — F28388D evaluation module for C2000™ MCU controlCARD™
  2. TMDSHSECDOCK — HSEC180 controlCARD baseboard docking station

Connections:

  1. PIN49-EPWM1A
  2. PIN51-GPIO1
  3. PIN50-EPWM3A
  4. PIN55-GPIO3
Experimental Environment: TMDSCNCD28388D + TMDSHSECDOCKFigure 4-2 Experimental Environment: TMDSCNCD28388D + TMDSHSECDOCK