SPRADT4 July   2025 TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   Abstract
  3. 1Introduction and Functional Block Diagram of TMS320F2838xD
  4. 2Limitations of Data Transfer Between CPU2 and CPU1.CLA1 via the IPC Module
  5. 3Principle of Data Transfer Between CPU2 and CPU1.CLA1 Using "IO Trigger + DMA Transfer"
  6. 4Verification of the "IO Trigger + DMA Transfer" Method
    1. 4.1 Timing Description and Code Implementation
    2. 4.2 Experimental Setup
    3. 4.3 Timing Waveform Verification
  7. 5Summary
  8. 6References

4.3 Timing Waveform Verification

IO Trigger + DMA Transfer — Experimental WaveformsFigure 4-3 IO Trigger + DMA Transfer — Experimental Waveforms
IO Trigger + DMA Transfer — Experimental TimingFigure 4-4 IO Trigger + DMA Transfer — Experimental Timing

Figure 4-4 illustrates the timing verification waveforms for data transfer between CPU2 and CPU1.CLA1 using the "IO trigger + DMA transfer" method. From the completion of data writing (time t1) to the end of the DMA transfer (time t2), the duration is approximately 600ns. Compared with the IPC approach, this method achieves the system's fast data transfer requirements without increasing CPU1 overhead.