SPRADT4 July   2025 TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   Abstract
  3. 1Introduction and Functional Block Diagram of TMS320F2838xD
  4. 2Limitations of Data Transfer Between CPU2 and CPU1.CLA1 via the IPC Module
  5. 3Principle of Data Transfer Between CPU2 and CPU1.CLA1 Using "IO Trigger + DMA Transfer"
  6. 4Verification of the "IO Trigger + DMA Transfer" Method
    1. 4.1 Timing Description and Code Implementation
    2. 4.2 Experimental Setup
    3. 4.3 Timing Waveform Verification
  7. 5Summary
  8. 6References

2 Limitations of Data Transfer Between CPU2 and CPU1.CLA1 via the IPC Module

Since there is no shared RAM space between CPU2 and CPU1.CLA1, the conventional approach to enable data interaction between them is through the IPC module.

First, CPU2 can transfer data to MSGRAMx/GSx RAM via the IPC module (CPU1-CPU2 IPC). Then, CPU1 can use CPU1.DMA module to move the data from MSGRAMx/GSx RAM to the DMA-CLA1 MSGRAM. Finally, CPU1.CLA1 accesses the DMA-CLA1 MSGRAM to read the data and perform subsequent processing in CLA1.

Data Flow: IPC-Based Data Interaction Between CPU2 and CPU1.CLA1Figure 2-1 Data Flow: IPC-Based Data Interaction Between CPU2 and CPU1.CLA1

Figure 2-2 illustrates the specific procedure for data transfer between CPU2 and CPU1.CLA1 using the IPC module:

  1. CPU2 first writes the data to be transferred to CLA1 into the MSG RAMx/GSx RAM.
  2. CPU2 writes a 1 to the C2TOC1IPCSET register, setting the C2TOC1IPCFLG bit to 1. Since the C2TOC1IPCFLG register in CPU2 and the C2TOC1IPCSTS register in CPU1 map to the same physical address, the C2TOC1IPCSTS bit in CPU1 is also set to 1. This simultaneously triggers an IPC interrupt to CPU1, notifying CPU1 that the data is ready and that it can proceed to the next step.
  3. CPU1 detects that the C2TOC1IPCSTS bit is set to 1.
  4. CPU1 begins reading data from MSG RAMx/GSx RAM and simultaneously initiates a DMA task. Through CPU1's DMA function, the data is transferred from MSG RAMx/GSx RAM to the DMA-CLA1 MSGRAM.
  5. CPU1 sets the C2TOC1IPCACK register to 1 to acknowledge receipt of the data. It then clears the flag bits in both C2TOC1IPCFLG and C2TOC1IPCSTS, completing the data transfer procedure.
IPC-Based Data Interaction Between CPU2 and CPU1.CLA1Figure 2-2 IPC-Based Data Interaction Between CPU2 and CPU1.CLA1

Based on the above analysis, since data interaction between CPU2 and CPU1 is implemented via the IPC module, CPU1 is required to perform steps 3 through 5 during the process, which adds significant overhead to CPU1. Therefore, when CPU1 is handling time-sensitive tasks or operating under heavy load, the IPC-based approach for data transfer between CPU2 and CPU1.CLA1 exhibits certain limitations.

As shown in Figure 2-3, the time required for CPU1 to complete steps 3 through 5 results in an overhead of approximately 2.93μs.

CPU1 Overhead Using the IPC MethodFigure 2-3 CPU1 Overhead Using the IPC Method