SPRADT4 July   2025 TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   Abstract
  3. 1Introduction and Functional Block Diagram of TMS320F2838xD
  4. 2Limitations of Data Transfer Between CPU2 and CPU1.CLA1 via the IPC Module
  5. 3Principle of Data Transfer Between CPU2 and CPU1.CLA1 Using "IO Trigger + DMA Transfer"
  6. 4Verification of the "IO Trigger + DMA Transfer" Method
    1. 4.1 Timing Description and Code Implementation
    2. 4.2 Experimental Setup
    3. 4.3 Timing Waveform Verification
  7. 5Summary
  8. 6References

Abstract

This document was translated from a simplified Chinese source. (ZHCAFM7)

In multi-core processor systems, the timeliness and accuracy of data transfers between cores are critical for realizing real-time control systems. In the 2838xD device, the absence of shared RAM space between CPU2 and CPU1.CLA1 poses a challenge for achieving fast data interaction between them. This paper analyzes the limitations of conventional IPC-based data transfer methods and, by leveraging the existing peripheral resources of the 28388D, proposes an "IO trigger + DMA transfer" approach to enable real-time, high-speed data interaction between CPU2 and CPU1.CLA1. Furthermore, this method is also applicable to processors with architectures similar to the 2838xD, such as the F28P65, facilitating fast inter-core data interaction in multi-core processors.