SPRADT4 July   2025 TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   Abstract
  3. 1Introduction and Functional Block Diagram of TMS320F2838xD
  4. 2Limitations of Data Transfer Between CPU2 and CPU1.CLA1 via the IPC Module
  5. 3Principle of Data Transfer Between CPU2 and CPU1.CLA1 Using "IO Trigger + DMA Transfer"
  6. 4Verification of the "IO Trigger + DMA Transfer" Method
    1. 4.1 Timing Description and Code Implementation
    2. 4.2 Experimental Setup
    3. 4.3 Timing Waveform Verification
  7. 5Summary
  8. 6References

1 Introduction and Functional Block Diagram of TMS320F2838xD

The TMS320F2838xD is a high-performance C2000 product featuring a multi-core architecture. It integrates two 200MHz C28 cores, two 200MHz CLA cores, and an ARM core, enabling multi-axis motor control with EtherCAT support.

In a dual-axis servo control system, one typical application scenario assigns CPU1 for EtherCAT control, while CPU1.CLA and CPU2 handle motor control for separate axes. Since encoder decoding requires the CLB and SPI modules, CPU2 is responsible for receiving encoder signals from both axes. After CPU2 receives the encoder data, it must rapidly transmit the data to CPU1.CLA to ensure precise real-time motor control.

Figure 1-1 shows the functional block diagram of the TMS320F28388D. Shared Message RAM exists between CPU2 and CPU1, allowing fast data interaction via IPC-triggered synchronization commands. However, there is no shared RAM space between CPU1.CLA1 and CPU2. As a result, CPU1.CLA1 and CPU2 cannot access the same memory space via their respective data buses, making rapid data interaction between CPU1.CLA1 and CPU2 difficult to achieve.

TMS320F28388D Functional Block Diagram — No Shared RAM Between CPU1.CLA1 and CPU2Figure 1-1 TMS320F28388D Functional Block Diagram — No Shared RAM Between CPU1.CLA1 and CPU2