SPRADT4 July   2025 TMS320F28388D , TMS320F28388S

 

  1.   1
  2.   Abstract
  3. 1Introduction and Functional Block Diagram of TMS320F2838xD
  4. 2Limitations of Data Transfer Between CPU2 and CPU1.CLA1 via the IPC Module
  5. 3Principle of Data Transfer Between CPU2 and CPU1.CLA1 Using "IO Trigger + DMA Transfer"
  6. 4Verification of the "IO Trigger + DMA Transfer" Method
    1. 4.1 Timing Description and Code Implementation
    2. 4.2 Experimental Setup
    3. 4.3 Timing Waveform Verification
  7. 5Summary
  8. 6References

5 Summary

To address the requirement for fast data interaction between CPU2 and CLA1 in the 28388D device, this work proposes an innovative method that leverages existing on-chip peripherals by utilizing GPIO-triggered DMA interrupts. This approach effectively resolves the difficulties and latency issues associated with data exchange between CPU2 and CPU1.CLA1. By employing available resources, the method fulfills customer requirements. The proposed concept is not only applicable to the 28388D/28385D but can also be extended to solve inter-core data interaction challenges in other multi-core MCUs with similar architectures.