SPRADT8 July   2026 AWR2188

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2AWR2188 CSI2 Hardware Interface
  6. 3AWR2188 CSI2 Output Configuration
    1. 3.1 Hardware-Related Configuration of CSI2
    2. 3.2 CSI2 Output Data Content Configuration
  7. 4CSI2 Output Data Format Examples
    1. 4.1 CP Data Format
    2. 4.2 CQ Data Format
    3. 4.3 Example of CSI2 Output Data Format in Sensor Mode
    4. 4.4 Example of CSI2 Output Data Format in Continuous Wave (CW) Mode
  8. 5Conclusion
  9. 6References

2 AWR2188 CSI2 Hardware Interface

The CSI2 interface of AWR2188 ES2.0 consists of five pairs of differential signals, supporting up to four data lanes and one clock lane.

Table 2-1 AWR2243 CSI2 Pin[1]
Signal Name Pin Type Description Pin Number
CSI2A_TXM0 Output Lane 0 differential output negative V1
CSI2A_TXM1 Output Lane 1 differential output negative T1
CSI2A_CLKM Output Differential clock output negative Y1
CSI2A_TXM2 Output Lane 2 differential output negative AE1
CSI2A_TXM3 Output Lane 3 differential output negative AC2
CSI2A_TXP0 Output Lane 0 differential output positive U1
CSI2A_TXP1 Output Lane 1 differential output positive R1
CSI2A_CLKP Output Differential clock output positive W1
CSI2A_TXP2 Output Lane 2 differential output positive AE2
CSI2A_TXP3 Output Lane 3 differential output positive AC1

The function of these five pairs of differential signals is software configurable. Two pairs of differential signal hardware pins, V1/U1 and Y1/W1, are fixed to Lane 0 and the clock lane, respectively. Other pins for differential pairs can be set to Lane 1, Lane 2, or Lane 3, but the same lane cannot be configured repeatedly.

Table 2-2 Correspondence Between CSI2 Hardware Pin and Lane Position
Lane Position AWR2188 Associated Pin CSI2 Functionality
M_ML_MSS_CSI2_LANE_POSITION_1 V1/U1 Fixed to Lane 0
M_ML_MSS_CSI2_LANE_POSITION_2 T1/R1 Can be configured to Lane 1, Lane 2, or Lane 3
M_ML_MSS_CSI2_LANE_POSITION_3 Y1/W1 Fixed to the clock lane
M_ML_MSS_CSI2_LANE_POSITION_4 AE1/AE2 Can be configured to Lane 1, Lane 2, or Lane 3
M_ML_MSS_CSI2_LANE_POSITION_5 AC2/AC1 Can be configured to Lane 1, Lane 2, or Lane 3

In addition to providing the AWR2188 chip, TI also provides the AWR2188 satellite radar reference design for user reference[2]. The hardware connection diagram of AWR2188 CSI2 is shown in Figure 2-1.

AWR2188 Satellite Radar Reference Design - CSI2 Connection DiagramFigure 2-1 AWR2188 Satellite Radar Reference Design - CSI2 Connection Diagram