SPRADT8 July   2026 AWR2188

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2AWR2188 CSI2 Hardware Interface
  6. 3AWR2188 CSI2 Output Configuration
    1. 3.1 Hardware-Related Configuration of CSI2
    2. 3.2 CSI2 Output Data Content Configuration
  7. 4CSI2 Output Data Format Examples
    1. 4.1 CP Data Format
    2. 4.2 CQ Data Format
    3. 4.3 Example of CSI2 Output Data Format in Sensor Mode
    4. 4.4 Example of CSI2 Output Data Format in Continuous Wave (CW) Mode
  8. 5Conclusion
  9. 6References

3.1 Hardware-Related Configuration of CSI2

The c_HsIfALaneConfig and w_LaneCfg parameters in T_ML_MSS_DATAPATH_CFG are used to configure the CSI2 pin functionality of the AWR2188.

The c_HsIfALaneConfig parameter enables single or multiple data lanes for CSI2. To maximize the CSI2 data throughput, users typically enable all data lanes. However, if the back-end chip supports a limited number of lanes, the AWR2188 can be used together by reducing the number of enabled lanes.

The w_LaneCfg parameter matches CSI2 lanes to specific functionalities and sets the polarity of each lane. The user’s hardware pin connection design must be aligned with software configuration, while the correct lane polarity is set depending on the requirements of the back-end chip to get correct CSI2 data.

The CSI2 connection of the AWR2188 satellite radar reference design mentioned in the previous section is based on the CSI2 pin functionality configuration shown in Table 3-1 and Table 3-2.

Table 3-1 AWR2188 Satellite Radar Reference Design - c_HsIfALaneConfig Configuration Example
Bit Lane Configuration Meaning
BIT[0] Lane 0 1 Enable Lane 0
BIT[1] Lane 1 1 Enable Lane 1
BIT[2] Lane 2 1 Enable Lane 2
BIT[3] Lane 3 1 Enable Lane 3
BIT[7:4] Reserved / /
Table 3-2 AWR2188 Satellite Radar Reference Design - w_LaneCfg Configuration Example
Parameter Bit Value Meaning
Lane 0 position BIT[2:0] 1 Position 1
Lane 0 polarity BIT[3] 0 Lane 0 polarity order: Positive -> negative
Lane 1 position BIT[6:4] 2 Position 2
Lane 1 polarity BIT[7] 0 Lane 1 polarity order: Positive -> negative
Lane 2 position BIT[10:8] 4 Position 4
Lane 2 polarity BIT[11] 0 Lane 2 polarity order: Positive -> negative
Lane 3 position BIT[14:12] 5 Position 5
Lane 3 polarity BIT[15] 0 Lane 3 polarity order: Positive -> negative
Clock lane position BIT[18:16] 3 Position 3
Clock lane polarity BIT[19] 0 Clock lane polarity order: Positive -> negative
Reserved BIT[31:19] / Reserved