SPRSP57F April   2020  – June 2026 DRA821U , DRA821U-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
        2. 5.3.2.2 DDRSS Mapping
      3. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
        2. 5.3.3.2 WKUP Domain
      4. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 MCU Domain
        3. 5.3.4.3 WKUP Domain
      5. 5.3.5  I3C
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
        2. 5.3.6.2 MCU Domain
      7. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
        2. 5.3.7.2 MCU Domain
      8. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
        2. 5.3.8.2 MCU Domain
        3. 5.3.8.3 WKUP Domain
      9. 5.3.9  MDIO
        1. 5.3.9.1 MCU Domain
        2. 5.3.9.2 MAIN Domain
      10. 5.3.10 CPSW2G
        1. 5.3.10.1 MCU Domain
      11. 5.3.11 CPSW5G
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 ECAP
        1. 5.3.12.1 MAIN Domain
      13. 5.3.13 EQEP
        1. 5.3.13.1 MAIN Domain
      14. 5.3.14 EPWM
        1. 5.3.14.1 MAIN Domain
      15. 5.3.15 USB
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 SERDES
        1. 5.3.16.1 MAIN Domain
      17. 5.3.17 OSPI
        1. 5.3.17.1 MCU Domain
      18. 5.3.18 Hyperbus
        1. 5.3.18.1 MCU Domain
      19. 5.3.19 GPMC
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 MMC
        1. 5.3.20.1 MAIN Domain
      21. 5.3.21 CPTS
        1. 5.3.21.1 MAIN Domain
        2. 5.3.21.2 MCU Domain
      22. 5.3.22 MCASP
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 DMTIMER
        1. 5.3.23.1 MAIN Domain
        2. 5.3.23.2 MCU Domain
      24. 5.3.24 Emulation and Debug
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 System and Miscellaneous
        1. 5.3.25.1 Boot Mode Configuration
          1. 5.3.25.1.1 MAIN Domain
          2. 5.3.25.1.2 MCU Domain
        2. 5.3.25.2 Clock
          1. 5.3.25.2.1 MAIN Domain
          2. 5.3.25.2.2 WKUP Domain
        3. 5.3.25.3 System
          1. 5.3.25.3.1 MAIN Domain
          2. 5.3.25.3.2 WKUP Domain
          3. 5.3.25.3.3 VMON
        4. 5.3.25.4 EFUSE
      26. 5.3.26 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Power-On-Hours (POH)
    5. 6.5  Operating Performance Points
    6. 6.6  Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  ADC12BT Electrical Characteristics
      7. 6.6.7  LVCMOS Electrical Characteristics
      8. 6.6.8  USB2PHY Electrical Characteristics
      9. 6.6.9  SERDES Electrical Characteristics
      10. 6.6.10 DDR Electrical Characteristics
    7. 6.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8  Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Sequencing
        1. 6.10.2.1  Power Supply Slew Rate Requirement
        2. 6.10.2.2  Combined MCU and Main Domains Power- Up Sequencing
        3. 6.10.2.3  Combined MCU and Main Domains Power- Down Sequencing - Option 1
        4. 6.10.2.4  Combined MCU and Main Domains Power- Down Sequencing - Option 2
        5. 6.10.2.5  Independent MCU and Main Domains Power- Up Sequencing
        6. 6.10.2.6  Independent MCU and Main Domains Power- Down Sequencing - Option 1
        7. 6.10.2.7  Independent MCU and Main Domains Power- Down Sequencing - Option 2
        8. 6.10.2.8  Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        9. 6.10.2.9  Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        10. 6.10.2.10 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input Clocks / Oscillators
          1. 6.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.10.4.1.3.1 Load Capacitance
            2. 6.10.4.1.3.2 Shunt Capacitance
          4. 6.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.10.4.1.5 Auxiliary OSC1 Not Used
          6. 6.10.4.1.6 WKUP_LF_CLKIN Internal Oscillator Clock Source
          7. 6.10.4.1.7 WKUP_LF_CLKIN Not Used
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 6.10.4.5 Interface Clock Specifications
          1. 6.10.4.5.1 Interface Clock Terminology
          2. 6.10.4.5.2 Interface Clock Frequency
      5. 6.10.5 Peripherals
        1. 6.10.5.1  ATL
          1. 6.10.5.1.1 ATL_PCLK Timing Requirements
          2. 6.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.10.5.2  CPSW2G
          1. 6.10.5.2.1 CPSW2G RMII Timings
            1. 6.10.5.2.1.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 6.10.5.2.1.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 6.10.5.2.1.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          2. 6.10.5.2.2 CPSW2G RGMII Timings
            1. 6.10.5.2.2.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 6.10.5.2.2.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.2.2.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 6.10.5.2.2.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        3. 6.10.5.3  CPSW5G
          1. 6.10.5.3.1 CPSW5G MDIO Interface Timings
          2. 6.10.5.3.2 CPSW5G RMII Timings
            1. 6.10.5.3.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 6.10.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 6.10.5.3.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 6.10.5.3.3 CPSW5G RGMII Timings
            1. 6.10.5.3.3.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 6.10.5.3.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 6.10.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        4. 6.10.5.4  DDRSS
        5. 6.10.5.5  ECAP
          1. 6.10.5.5.1 Timing Requirements for ECAP
          2. 6.10.5.5.2 Switching Characteristics for ECAP
        6. 6.10.5.6  EPWM
          1. 6.10.5.6.1 Timing Requirements for EPWM
          2. 6.10.5.6.2 Switching Characteristics for EPWM
        7. 6.10.5.7  EQEP
          1. 6.10.5.7.1 Timing Requirements for EQEP
          2. 6.10.5.7.2 Switching Characteristics for EQEP
        8. 6.10.5.8  GPIO
        9. 6.10.5.9  GPMC
          1. 6.10.5.9.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.10.5.9.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.10.5.9.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.10.5.9.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.10.5.9.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.9.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.10.5.9.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.10.5.9.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.9.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        10. 6.10.5.10 HyperBus
          1. 6.10.5.10.1 Timing Requirements for HyperBus Initialization
          2. 6.10.5.10.2 HyperBus 166 MHz Switching Characteristics
          3. 6.10.5.10.3 HyperBus 100 MHz Switching Characteristics
        11. 6.10.5.11 I2C
        12. 6.10.5.12 I3C
        13. 6.10.5.13 MCAN
        14. 6.10.5.14 MCASP
          1. 6.10.5.14.1 Timing Requirements for MCASP
        15. 6.10.5.15 MCSPI
          1. 6.10.5.15.1 MCSPI — Controller Mode
          2. 6.10.5.15.2 MCSPI — Peripheral Mode
        16. 6.10.5.16 eMMC/SD/SDIO
          1. 6.10.5.16.1 MMCSD0 - eMMC Interface
            1. 6.10.5.16.1.1 Legacy SDR Mode
            2. 6.10.5.16.1.2 High Speed SDR Mode
            3. 6.10.5.16.1.3 High Speed DDR Mode
            4. 6.10.5.16.1.4 HS200 Mode
            5. 6.10.5.16.1.5 HS400 Mode
          2. 6.10.5.16.2 MMCSDi — MMCSD1 — SD/SDIO Interface
            1. 6.10.5.16.2.1 Default speed Mode
            2. 6.10.5.16.2.2 High Speed Mode
            3. 6.10.5.16.2.3 UHS–I SDR12 Mode
            4. 6.10.5.16.2.4 UHS–I SDR25 Mode
            5. 6.10.5.16.2.5 UHS–I SDR50 Mode
            6. 6.10.5.16.2.6 UHS–I DDR50 Mode
            7. 6.10.5.16.2.7 UHS–I SDR104 Mode
        17. 6.10.5.17 NAVSS
          1. 6.10.5.17.1 Timing Requirements for CPTS Input
          2. 6.10.5.17.2 Switching Characteristics for CPTS Output
        18. 6.10.5.18 OSPI
          1. 6.10.5.18.1 OSPI With Data Training
            1. 6.10.5.18.1.1 OSPI Switching Characteristics – Data Training
          2. 6.10.5.18.2 OSPI Without Data Training
            1. 6.10.5.18.2.1 OSPI Switching Characteristics – DDR Mode
            2. 6.10.5.18.2.2 OSPI Switching Characteristics – SDR Mode
            3. 6.10.5.18.2.3 OSPI Timing Requirements – DDR Mode
            4. 6.10.5.18.2.4 OSPI Timing Requirements – SDR Mode
        19. 6.10.5.19 PCIE
        20. 6.10.5.20 Timers
          1. 6.10.5.20.1 Timing Requirements for Timers
          2. 6.10.5.20.2 Switching Characteristics for Timers
        21. 6.10.5.21 UART
          1. 6.10.5.21.1 UART Timing Requirements
          2. 6.10.5.21.2 UART Switching Characteristics
        22. 6.10.5.22 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Debug Trace
        2. 6.10.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
          1. 6.10.6.2.1 JTAG Electrical Data and Timing
            1. 6.10.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG
            2. 6.10.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
    3. 7.3 Other Subsystems
      1. 7.3.1 MSMC
      2. 7.3.2 NAVSS
        1. 7.3.2.1 NAVSS0
        2. 7.3.2.2 MCU_NAVSS
      3. 7.3.3 PDMA Controller
      4. 7.3.4 Peripherals
        1. 7.3.4.1  ADC
        2. 7.3.4.2  ATL
        3. 7.3.4.3  CPSW2G
        4. 7.3.4.4  CPSW5G
        5. 7.3.4.5  DCC
        6. 7.3.4.6  DDRSS
        7. 7.3.4.7  ECAP
        8. 7.3.4.8  EPWM
        9. 7.3.4.9  ELM
        10. 7.3.4.10 ESM
        11. 7.3.4.11 EQEP
        12. 7.3.4.12 GPIO
        13. 7.3.4.13 GPMC
        14. 7.3.4.14 Hyperbus
        15. 7.3.4.15 I2C
        16. 7.3.4.16 I3C
        17. 7.3.4.17 MCAN
        18. 7.3.4.18 MCASP
        19. 7.3.4.19 MCRC Controller
        20. 7.3.4.20 MCSPI
        21. 7.3.4.21 MMC/SD
        22. 7.3.4.22 OSPI
        23. 7.3.4.23 PCIE
        24. 7.3.4.24 SerDes
        25. 7.3.4.25 WWDT
        26. 7.3.4.26 Timers
        27. 7.3.4.27 UART
        28. 7.3.4.28 USB
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 Device Connection and Layout Fundamentals
      1. 8.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.2.1.1 Power Distribution Network Implementation Guidance
      2. 8.2.2 External Oscillator
      3. 8.2.3 JTAG and EMU
      4. 8.2.4 Reset
      5. 8.2.5 Unused Pins
      6. 8.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 8.3 Peripheral- and Interface-Specific Design Information
      1. 8.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.3.2.1 No Loopback and Internal Pad Loopback
        2. 8.3.2.2 External Board Loopback
        3. 8.3.2.3 DQS (only available in Octal Flash devices)
      3. 8.3.3 USB VBUS Design Guidelines
      4. 8.3.4 System Power Supply Monitor Design Guidelines
      5. 8.3.5 High Speed Differential Signal Routing Guidance
      6. 8.3.6 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

1 Features

Processor cores:

  • Dual 64-bit Arm®Cortex®-A72 microprocessor subsystem at up to 2.0GHz
    • 1MB L2 shared cache per dual-core Cortex®-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm®Cortex®-R5F MCUs at up to 1.0GHz with optional lockstep operation
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm®Cortex®-R5F MCUs in isolated MCU subsystem
    • 2× Arm®Cortex®-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm®Cortex®-A72
  • Independent processing subsystems with Arm®Cortex®-A72, Arm®Cortex®-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA

  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1

  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express® Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C®)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital® 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB