SPRSP57F April   2020  – June 2026 DRA821U , DRA821U-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
        2. 5.3.2.2 DDRSS Mapping
      3. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
        2. 5.3.3.2 WKUP Domain
      4. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 MCU Domain
        3. 5.3.4.3 WKUP Domain
      5. 5.3.5  I3C
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
        2. 5.3.6.2 MCU Domain
      7. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
        2. 5.3.7.2 MCU Domain
      8. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
        2. 5.3.8.2 MCU Domain
        3. 5.3.8.3 WKUP Domain
      9. 5.3.9  MDIO
        1. 5.3.9.1 MCU Domain
        2. 5.3.9.2 MAIN Domain
      10. 5.3.10 CPSW2G
        1. 5.3.10.1 MCU Domain
      11. 5.3.11 CPSW5G
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 ECAP
        1. 5.3.12.1 MAIN Domain
      13. 5.3.13 EQEP
        1. 5.3.13.1 MAIN Domain
      14. 5.3.14 EPWM
        1. 5.3.14.1 MAIN Domain
      15. 5.3.15 USB
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 SERDES
        1. 5.3.16.1 MAIN Domain
      17. 5.3.17 OSPI
        1. 5.3.17.1 MCU Domain
      18. 5.3.18 Hyperbus
        1. 5.3.18.1 MCU Domain
      19. 5.3.19 GPMC
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 MMC
        1. 5.3.20.1 MAIN Domain
      21. 5.3.21 CPTS
        1. 5.3.21.1 MAIN Domain
        2. 5.3.21.2 MCU Domain
      22. 5.3.22 MCASP
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 DMTIMER
        1. 5.3.23.1 MAIN Domain
        2. 5.3.23.2 MCU Domain
      24. 5.3.24 Emulation and Debug
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 System and Miscellaneous
        1. 5.3.25.1 Boot Mode Configuration
          1. 5.3.25.1.1 MAIN Domain
          2. 5.3.25.1.2 MCU Domain
        2. 5.3.25.2 Clock
          1. 5.3.25.2.1 MAIN Domain
          2. 5.3.25.2.2 WKUP Domain
        3. 5.3.25.3 System
          1. 5.3.25.3.1 MAIN Domain
          2. 5.3.25.3.2 WKUP Domain
          3. 5.3.25.3.3 VMON
        4. 5.3.25.4 EFUSE
      26. 5.3.26 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Power-On-Hours (POH)
    5. 6.5  Operating Performance Points
    6. 6.6  Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  ADC12BT Electrical Characteristics
      7. 6.6.7  LVCMOS Electrical Characteristics
      8. 6.6.8  USB2PHY Electrical Characteristics
      9. 6.6.9  SERDES Electrical Characteristics
      10. 6.6.10 DDR Electrical Characteristics
    7. 6.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8  Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Sequencing
        1. 6.10.2.1  Power Supply Slew Rate Requirement
        2. 6.10.2.2  Combined MCU and Main Domains Power- Up Sequencing
        3. 6.10.2.3  Combined MCU and Main Domains Power- Down Sequencing - Option 1
        4. 6.10.2.4  Combined MCU and Main Domains Power- Down Sequencing - Option 2
        5. 6.10.2.5  Independent MCU and Main Domains Power- Up Sequencing
        6. 6.10.2.6  Independent MCU and Main Domains Power- Down Sequencing - Option 1
        7. 6.10.2.7  Independent MCU and Main Domains Power- Down Sequencing - Option 2
        8. 6.10.2.8  Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        9. 6.10.2.9  Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        10. 6.10.2.10 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input Clocks / Oscillators
          1. 6.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.10.4.1.3.1 Load Capacitance
            2. 6.10.4.1.3.2 Shunt Capacitance
          4. 6.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.10.4.1.5 Auxiliary OSC1 Not Used
          6. 6.10.4.1.6 WKUP_LF_CLKIN Internal Oscillator Clock Source
          7. 6.10.4.1.7 WKUP_LF_CLKIN Not Used
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 6.10.4.5 Interface Clock Specifications
          1. 6.10.4.5.1 Interface Clock Terminology
          2. 6.10.4.5.2 Interface Clock Frequency
      5. 6.10.5 Peripherals
        1. 6.10.5.1  ATL
          1. 6.10.5.1.1 ATL_PCLK Timing Requirements
          2. 6.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.10.5.2  CPSW2G
          1. 6.10.5.2.1 CPSW2G RMII Timings
            1. 6.10.5.2.1.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 6.10.5.2.1.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 6.10.5.2.1.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          2. 6.10.5.2.2 CPSW2G RGMII Timings
            1. 6.10.5.2.2.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 6.10.5.2.2.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.2.2.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 6.10.5.2.2.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        3. 6.10.5.3  CPSW5G
          1. 6.10.5.3.1 CPSW5G MDIO Interface Timings
          2. 6.10.5.3.2 CPSW5G RMII Timings
            1. 6.10.5.3.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 6.10.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 6.10.5.3.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 6.10.5.3.3 CPSW5G RGMII Timings
            1. 6.10.5.3.3.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 6.10.5.3.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 6.10.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        4. 6.10.5.4  DDRSS
        5. 6.10.5.5  ECAP
          1. 6.10.5.5.1 Timing Requirements for ECAP
          2. 6.10.5.5.2 Switching Characteristics for ECAP
        6. 6.10.5.6  EPWM
          1. 6.10.5.6.1 Timing Requirements for EPWM
          2. 6.10.5.6.2 Switching Characteristics for EPWM
        7. 6.10.5.7  EQEP
          1. 6.10.5.7.1 Timing Requirements for EQEP
          2. 6.10.5.7.2 Switching Characteristics for EQEP
        8. 6.10.5.8  GPIO
        9. 6.10.5.9  GPMC
          1. 6.10.5.9.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.10.5.9.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.10.5.9.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.10.5.9.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.10.5.9.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.9.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.10.5.9.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.10.5.9.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.9.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        10. 6.10.5.10 HyperBus
          1. 6.10.5.10.1 Timing Requirements for HyperBus Initialization
          2. 6.10.5.10.2 HyperBus 166 MHz Switching Characteristics
          3. 6.10.5.10.3 HyperBus 100 MHz Switching Characteristics
        11. 6.10.5.11 I2C
        12. 6.10.5.12 I3C
        13. 6.10.5.13 MCAN
        14. 6.10.5.14 MCASP
          1. 6.10.5.14.1 Timing Requirements for MCASP
        15. 6.10.5.15 MCSPI
          1. 6.10.5.15.1 MCSPI — Controller Mode
          2. 6.10.5.15.2 MCSPI — Peripheral Mode
        16. 6.10.5.16 eMMC/SD/SDIO
          1. 6.10.5.16.1 MMCSD0 - eMMC Interface
            1. 6.10.5.16.1.1 Legacy SDR Mode
            2. 6.10.5.16.1.2 High Speed SDR Mode
            3. 6.10.5.16.1.3 High Speed DDR Mode
            4. 6.10.5.16.1.4 HS200 Mode
            5. 6.10.5.16.1.5 HS400 Mode
          2. 6.10.5.16.2 MMCSDi — MMCSD1 — SD/SDIO Interface
            1. 6.10.5.16.2.1 Default speed Mode
            2. 6.10.5.16.2.2 High Speed Mode
            3. 6.10.5.16.2.3 UHS–I SDR12 Mode
            4. 6.10.5.16.2.4 UHS–I SDR25 Mode
            5. 6.10.5.16.2.5 UHS–I SDR50 Mode
            6. 6.10.5.16.2.6 UHS–I DDR50 Mode
            7. 6.10.5.16.2.7 UHS–I SDR104 Mode
        17. 6.10.5.17 NAVSS
          1. 6.10.5.17.1 Timing Requirements for CPTS Input
          2. 6.10.5.17.2 Switching Characteristics for CPTS Output
        18. 6.10.5.18 OSPI
          1. 6.10.5.18.1 OSPI With Data Training
            1. 6.10.5.18.1.1 OSPI Switching Characteristics – Data Training
          2. 6.10.5.18.2 OSPI Without Data Training
            1. 6.10.5.18.2.1 OSPI Switching Characteristics – DDR Mode
            2. 6.10.5.18.2.2 OSPI Switching Characteristics – SDR Mode
            3. 6.10.5.18.2.3 OSPI Timing Requirements – DDR Mode
            4. 6.10.5.18.2.4 OSPI Timing Requirements – SDR Mode
        19. 6.10.5.19 PCIE
        20. 6.10.5.20 Timers
          1. 6.10.5.20.1 Timing Requirements for Timers
          2. 6.10.5.20.2 Switching Characteristics for Timers
        21. 6.10.5.21 UART
          1. 6.10.5.21.1 UART Timing Requirements
          2. 6.10.5.21.2 UART Switching Characteristics
        22. 6.10.5.22 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Debug Trace
        2. 6.10.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
          1. 6.10.6.2.1 JTAG Electrical Data and Timing
            1. 6.10.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG
            2. 6.10.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
    3. 7.3 Other Subsystems
      1. 7.3.1 MSMC
      2. 7.3.2 NAVSS
        1. 7.3.2.1 NAVSS0
        2. 7.3.2.2 MCU_NAVSS
      3. 7.3.3 PDMA Controller
      4. 7.3.4 Peripherals
        1. 7.3.4.1  ADC
        2. 7.3.4.2  ATL
        3. 7.3.4.3  CPSW2G
        4. 7.3.4.4  CPSW5G
        5. 7.3.4.5  DCC
        6. 7.3.4.6  DDRSS
        7. 7.3.4.7  ECAP
        8. 7.3.4.8  EPWM
        9. 7.3.4.9  ELM
        10. 7.3.4.10 ESM
        11. 7.3.4.11 EQEP
        12. 7.3.4.12 GPIO
        13. 7.3.4.13 GPMC
        14. 7.3.4.14 Hyperbus
        15. 7.3.4.15 I2C
        16. 7.3.4.16 I3C
        17. 7.3.4.17 MCAN
        18. 7.3.4.18 MCASP
        19. 7.3.4.19 MCRC Controller
        20. 7.3.4.20 MCSPI
        21. 7.3.4.21 MMC/SD
        22. 7.3.4.22 OSPI
        23. 7.3.4.23 PCIE
        24. 7.3.4.24 SerDes
        25. 7.3.4.25 WWDT
        26. 7.3.4.26 Timers
        27. 7.3.4.27 UART
        28. 7.3.4.28 USB
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 Device Connection and Layout Fundamentals
      1. 8.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.2.1.1 Power Distribution Network Implementation Guidance
      2. 8.2.2 External Oscillator
      3. 8.2.3 JTAG and EMU
      4. 8.2.4 Reset
      5. 8.2.5 Unused Pins
      6. 8.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 8.3 Peripheral- and Interface-Specific Design Information
      1. 8.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.3.2.1 No Loopback and Internal Pad Loopback
        2. 8.3.2.2 External Board Loopback
        3. 8.3.2.3 DQS (only available in Octal Flash devices)
      3. 8.3.3 USB VBUS Design Guidelines
      4. 8.3.4 System Power Supply Monitor Design Guidelines
      5. 8.3.5 High Speed Differential Signal Routing Guidance
      6. 8.3.6 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

6.10.2.5 Independent MCU and Main Domains Power- Up Sequencing

Independent MCU and Main voltage domains enable an SoC’s MCU and Main processor sub-systems to operate independently. There are 2 reasons an SoC’s PDN design may need to support independent MCU and Main processor functionality. First is to provide flexibility to enable SoC low power modes that can significant reduce SoC power dissipation when processor operations are not needed. Second is to enable robustness to gain freedom from interference (FFI) of a single fault impacting both MCU and Main processor sub-systems which is especially beneficial if using the SoC’s MCU as the system safety monitoring processor. The number of additional PDN power rails needed is dependent upon number of different MCU IO signaling voltage levels. If only 1.8V IO signaling is used, the only 2 additional power rails could be required. If both 1.8 and 3.3V IO signaling is desired, then 4 additional power rails could be needed.

DRA821U-Q1 DRA821U Independent MCU and Main Domains, Primary Power-Up Sequence
A. Terminology:
  • Primary = Essential power up sequence of all voltage domains to full active state.
  • VOPR MIN = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.
  • Ramp Up = Voltage supply transition time from off condition to VOPR MIN.
  • Domain_“n” = multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0, VDDSHV1, VDDSHV2 … VDDSHV6)
  • Domain_“xxx” = different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx = VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)
Time stamp markers show approximate elapsed times that are dependent upon PDN feature set, component selection and power mapping. Values shown are typical for PDNs supporting independent MCU and Main voltage domains but could vary based upon PDN design.
Time Stamp definitions and (typical values for reference only):
T0 – All 3.3V voltages start supply ramp-up to VOPR MIN. (0 ms)
T1 – All 1.8V voltages start supply ramp-up to VOPR MIN. (2 ms)
T2 – All core voltages start supply ramp-up to VOPR MIN. (3 ms)
T3 – All RAM array voltages start supply ramp-up to VOPR MIN. (4 ms)
T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13 ms)
B. VDDSHVx 3.3V IO domains may have additional ramp-up delay due to following:
  1. Minimizing PMIC power dissipation during low power mode that includes disabling PMIC’s VIO_IN supply for GPIO output buffers.
  2. PDN component turn-on and ramp-up delays needed to isolate MCU and Main IO domains
C. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.
D. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.
E. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8 V) power rail is required for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed 3.3 V operation is acceptable, then domain can be grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO 1.8-V power rail.
F. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.
G. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy> domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.
H. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-line supply filter is allowed.
I. VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.
J. VDD_MCU is a digital voltage domain with a wide operational voltage range enabling it to be grouped either with VDDAR_MCU domain or with VDD_CORE; for the “Isolated MCU and Main Domains Power-Up Sequencing,” VDD_MCU can be grouped with VDDAR_MCU; VDD_MCU must be ramped-up before T2. If VDDAR_MCU is not grouped with VDD_MCU, it must be ramped at T3.
K. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings into registers during power up sequence.
L. Minimum elapsed time from crystal oscillator circuitry being energized (VDDA_OSC1 at T1) until stable clock frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values. A conservative 10-ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.
Figure 6-6 Independent MCU and Main Domains, Primary Power-Up Sequence