SPRSPB9B July   2025  – October 2025 F28E120SB , F28E120SC

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR and PWM X-BAR
      6. 5.4.6 GPIO and ADC Allocation
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Power Consumption Summary
      1. 6.4.1 System Current Consumption - Internal Supply
      2. 6.4.2 Operating Mode Test Description
      3. 6.4.3 Current Consumption Graphs
      4. 6.4.4 Reducing Current Consumption
    5. 6.5  Electrical Characteristics
    6. 6.6  Thermal Resistance Characteristics for PT Package
    7. 6.7  Thermal Resistance Characteristics for VFC Package
    8. 6.8  Thermal Resistance Characteristics for RHB Package
    9. 6.9  Thermal Design Considerations
    10. 6.10 System
      1. 6.10.1  Power Management Module (PMM)
        1. 6.10.1.1 Introduction
        2. 6.10.1.2 Overview
          1. 6.10.1.2.1 Power Rail Monitors
            1. 6.10.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.10.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
          2. 6.10.1.2.2 External Supervisor Usage
          3. 6.10.1.2.3 Delay Blocks
        3. 6.10.1.3 External Components
          1. 6.10.1.3.1 Decoupling Capacitors
            1. 6.10.1.3.1.1 VDDIO Decoupling
        4. 6.10.1.4 Power Sequencing
          1. 6.10.1.4.1 Supply Pins Ganging
          2. 6.10.1.4.2 Signal Pins Power Sequence
          3. 6.10.1.4.3 Supply Pins Power Sequence
            1. 6.10.1.4.3.1 Internal Power-Up Sequence
            2. 6.10.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 6.10.1.4.3.3 Supply Slew Rate
        5. 6.10.1.5 Recommended Operating Conditions Applicability to the PMM
        6. 6.10.1.6 Power Management Module Electrical Data and Timing
          1. 6.10.1.6.1 Power Management Module Operating Conditions
          2. 6.10.1.6.2 Power Management Module Characteristics
      2. 6.10.2  Reset Timing
        1. 6.10.2.1 Reset Sources
        2. 6.10.2.2 Reset Electrical Data and Timing
          1. 6.10.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.10.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.10.2.2.3 Reset Timing Diagrams
      3. 6.10.3  Clock Specifications
        1. 6.10.3.1 Clock Sources
        2. 6.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.10.3.2.1.1 Input Clock Frequency
            2. 6.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.10.3.2.1.3 X1 Timing Requirements
            4. 6.10.3.2.1.4 PLL Characteristics
            5. 6.10.3.2.1.5 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            6. 6.10.3.2.1.6 Internal Clock Frequencies
        3. 6.10.3.3 Input Clocks and PLLs
        4. 6.10.3.4 XTAL Oscillator
          1. 6.10.3.4.1 Introduction
          2. 6.10.3.4.2 Overview
            1. 6.10.3.4.2.1 Electrical Oscillator
              1. 6.10.3.4.2.1.1 Modes of Operation
                1. 6.10.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.10.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.10.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.10.3.4.2.2 Quartz Crystal
          3. 6.10.3.4.3 Functional Operation
            1. 6.10.3.4.3.1 ESR – Effective Series Resistance
            2. 6.10.3.4.3.2 Rneg – Negative Resistance
            3. 6.10.3.4.3.3 Start-up Time
              1. 6.10.3.4.3.3.1 X1/X2 Precondition
            4. 6.10.3.4.3.4 DL – Drive Level
          4. 6.10.3.4.4 How to Choose a Crystal
          5. 6.10.3.4.5 Testing
          6. 6.10.3.4.6 Common Problems and Debug Tips
          7. 6.10.3.4.7 Crystal Oscillator Specifications
            1. 6.10.3.4.7.1 Crystal Oscillator Parameters
            2. 6.10.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.10.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.10.3.5 Internal Oscillators
          1. 6.10.3.5.1 System Oscillator SYSOSC
          2. 6.10.3.5.2 Wide Range Oscillator WROSC
      4. 6.10.4  Flash Parameters
        1. 6.10.4.1 Flash Parameters 
      5. 6.10.5  RAM Specifications
      6. 6.10.6  ROM Specifications
      7. 6.10.7  Emulation/JTAG
        1. 6.10.7.1 JTAG Electrical Data and Timing
          1. 6.10.7.1.1 JTAG Timing Requirements
          2. 6.10.7.1.2 JTAG Switching Characteristics
          3. 6.10.7.1.3 JTAG Timing Diagram
        2. 6.10.7.2 cJTAG Electrical Data and Timing
          1. 6.10.7.2.1 cJTAG Timing Requirements
          2. 6.10.7.2.2 cJTAG Switching Characteristics
          3. 6.10.7.2.3 cJTAG Timing Diagram
      8. 6.10.8  GPIO Electrical Data and Timing
        1. 6.10.8.1 GPIO – Output Timing
          1. 6.10.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.10.8.1.2 General-Purpose Output Timing Diagram
        2. 6.10.8.2 GPIO – Input Timing
          1. 6.10.8.2.1 General-Purpose Input Timing Requirements
          2. 6.10.8.2.2 Sampling Mode
        3. 6.10.8.3 Sampling Window Width for Input Signals
      9. 6.10.9  Interrupts
        1. 6.10.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.10.9.1.1 External Interrupt Timing Requirements
          2. 6.10.9.1.2 External Interrupt Switching Characteristics
          3. 6.10.9.1.3 External Interrupt Timing
      10. 6.10.10 Low-Power Modes
        1. 6.10.10.1 Clock-Gating Low-Power Modes
        2. 6.10.10.2 Low-Power Mode Wake-up Timing
          1. 6.10.10.2.1 IDLE Mode Timing Requirements
          2. 6.10.10.2.2 IDLE Mode Switching Characteristics
          3. 6.10.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.10.10.2.4 STANDBY Mode Timing Requirements
          5. 6.10.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.10.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.10.10.2.7 HALT Mode Timing Requirements
          8. 6.10.10.2.8 HALT Mode Switching Characteristics
          9. 6.10.10.2.9 HALT Entry and Exit Timing Diagram
    11. 6.11 Analog Peripherals
      1. 6.11.1 Analog Pins and Internal Connections
      2. 6.11.2 Analog-to-Digital Converter (ADC)
        1. 6.11.2.1 ADC Configurability
          1. 6.11.2.1.1 Signal Mode
        2. 6.11.2.2 ADC Electrical Data and Timing
          1. 6.11.2.2.1 ADC Operating Conditions
          2. 6.11.2.2.2 ADC Characteristics
          3. 6.11.2.2.3 ADC INL and DNL
          4. 6.11.2.2.4 ADC Performance Per Pin
          5. 6.11.2.2.5 ADC Input Model
          6. 6.11.2.2.6 ADC Timing Diagrams
      3. 6.11.3 Comparator Subsystem (CMPSS_LITE)
        1. 6.11.3.1 COMPDACOUT
        2. 6.11.3.2 CMPSS Connectivity Diagram
        3. 6.11.3.3 Block Diagram
        4. 6.11.3.4 CMPSS Electrical Data and Timing
          1. 6.11.3.4.1 CMPSS_LITE Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.11.3.4.2 CMPSS_LITE DAC Static Electrical Characteristics
          4. 6.11.3.4.3 CMPSS Illustrative Graphs
          5. 6.11.3.4.4 Buffered Output from CMPx_LITE_DACL Operating Conditions
          6. 6.11.3.4.5 Buffered Output from CMPx_LITE_DACL Electrical Characteristics
      4. 6.11.4 Programmable Gain Amplifier (PGA)
        1. 6.11.4.1 PGA Electrical Data and Timing
          1. 6.11.4.1.1 PGA Operating Conditions
          2. 6.11.4.1.2 PGA Characteristics
      5. 6.11.5 Temperature Sensor
        1. 6.11.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.11.5.1.1 Temperature Sensor Characteristics
    12. 6.12 Control Peripherals
      1. 6.12.1 Multichannel Pulse Width Modulator (MCPWM)
        1. 6.12.1.1 Control Peripherals Synchronization
        2. 6.12.1.2 MCPWM Electrical Data and Timing
          1. 6.12.1.2.1 MCPWM Timing Requirements
          2. 6.12.1.2.2 MCPWM Switching Characteristics
          3. 6.12.1.2.3 Trip-Zone Input Timing
            1. 6.12.1.2.3.1 PWM Hi-Z Characteristics Timing Diagram
      2. 6.12.2 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.12.2.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.12.2.2 ADCSOCAO or ADCSOCBO Timing Diagram
      3. 6.12.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.12.3.1 eQEP Electrical Data and Timing
          1. 6.12.3.1.1 eQEP Timing Requirements
          2. 6.12.3.1.2 eQEP Switching Characteristics
      4. 6.12.4 Enhanced Capture (eCAP)
        1. 6.12.4.1 eCAP Block Diagram
        2. 6.12.4.2 eCAP Synchronization
        3. 6.12.4.3 eCAP Electrical Data and Timing
          1. 6.12.4.3.1 eCAP Switching Characteristics
    13. 6.13 Communications Peripherals
      1. 6.13.1 Inter-Integrated Circuit (I2C)
        1. 6.13.1.1 I2C Electrical Data and Timing
          1. 6.13.1.1.1 I2C Timing Requirements
          2. 6.13.1.1.2 I2C Switching Characteristics
          3. 6.13.1.1.3 I2C Timing Diagram
      2. 6.13.2 Universal Asynchronous Receiver-Transmitter (UART)
      3. 6.13.3 Serial Peripheral Interface (SPI)
        1. 6.13.3.1 SPI Controller Mode Timings
          1. 6.13.3.1.1 SPI Controller Mode Timing Requirements
          2. 6.13.3.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.13.3.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.13.3.1.4 SPI Controller Mode Timing Diagrams
        2. 6.13.3.2 SPI Peripheral Mode Timings
          1. 6.13.3.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.13.3.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.13.3.2.3 SPI Peripheral Mode Timing Diagrams
      4. 6.13.4 Serial Communications Interface (SCI)
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Memory
      1. 7.2.1 C28x Memory Map
        1. 7.2.1.1 Dedicated RAM (Mx RAM)
      2. 7.2.2 Flash Memory Map
      3. 7.2.3 Peripheral Registers Memory Map
    3. 7.3  Identification
    4. 7.4  C28x Processor
      1. 7.4.1 Floating-Point Unit (FPU)
    5. 7.5  Direct Memory Access (DMA)
    6. 7.6  Device Boot Modes
      1. 7.6.1 Device Boot Configurations
        1. 7.6.1.1 Configuring Boot Mode Pins
        2. 7.6.1.2 Configuring Boot Mode Table Options
      2. 7.6.2 GPIO Assignments
    7. 7.7  Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8  Watchdog
    9. 7.9  C28x Timers
    10. 7.10 Dual-Clock Comparator (DCC)
      1. 7.10.1 Features
      2. 7.10.2 Mapping of DCCx Clock Source Inputs
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     TAPE AND REEL INFORMATION

10 Revision History

Changes from September 9, 2025 to October 22, 2025 (from Revision A (September 2025) to Revision B (October 2025))

  • Features section: Changed ADC speed from 9.4 MSPS to 8.9 MSPS.Go
  • Device Comparison section: Changed ADC speed from 68.75 ns / 9.4 MSPS to 112.36 ns / 8.9 MSPS.Go
  • Device Comparison section: Removed "Internal 3.3-V to 1.2-V Voltage Regulator (VREG)" table row.Go
  • Power and Ground table: Added "Connect this pin to 3.3-V supply" to Description of VDD3VFL, VDDA, VDDIO, and VDDOSC.Go
  • GPIO and ADC Allocation table: Changed "F2800135V" to "64 VPM."Go
  • Changed typical VDDIO operating mode current consumption at 30 degrees from 32mA to 28mAGo
  • Changed typical VDDA operating mode current consumption at 30 degrees from 2.5mA to 3.3mAGo
  • Changed max VDDA operating mode current consumption at 125 degrees from 6.5mA to 7mAGo
  • Changed max VDDIO idle mode current consumption at 125 degrees from 27mA to 29mAGo
  • Changed typical VDDA idle mode current consumption at 30 degrees from 0.01mA to 2.5mAGo
  • Changed max VDDA standby mode (PLL Enabled) current consumption at 125 degrees from 0.1mA to 4.0mAGo
  • Changed typical VDDIO reset mode current consumption at 30 degrees from 8mA to 12.5mAGo
  • Changed typical VDDA reset mode current consumption at 30 degrees from 0.01mA to 1mAGo
  • Current Consumption Graphs section: Updated figures. Go
  • Current Consumption Graphs section: Added section.Go
  • PMM Block Diagram: Updated figure. Go
  • External Supervisor Usage section: Updated section to remove VDD mentions.Go
  • Internal Power-Up Sequence section: Updated title and section to remove VDD and VREG mentions.Go
  • Internal Power-Up Sequence Summary table: Updated title to remove VDD mention.Go
  • Recommended Operating Conditions Applicability to the PMM section: Updated section to remove VREG mention.Go
  • Changed min supply ramp rate from 20mV/us to 3mV/usGo
  • Changed power up time from 350us to 40usGo
  • Changed In-rush currrent from 80mA to 45mAGo
  • Changed XRSn release delay after supplies are ramped up from 40us to 320usGo
  • Changed XRSn release delay after VDDIO BOR event from 40us to 360usGo
  • Changed XRSn release delay after VDDIO POR event from 120us to 440usGo
  • Power-on Reset Diagram: Removed VDD from figure.Go
  • Changed max PLL Lock time from 15us to 786*tC(OSCLK) usGo
  • Changed min INTCLK frequency from 2MHz to 4MHzGo
  • Changed max INTCLK frequency from 20MHz to 25MHzGo
  • Changed min VCOCLK frequency from 220MHz to 160MHzGo
  • Changed max VCOCLK frequency from 600MHz to 400MHzGo
  • Changed min PLLRAWCLK frequency from 6MHz to 5MHzGo
  • Changed max PLLRAWCLK frequency from 240MHz to 200MHzGo
  • Changed nominal PLL Limp frequency formulaGo
  • Changed min LSPCLK period from 8.33ns to 6.25nsGo
  • Added WROSC frequency table Go
  • RAM Specifications section: Added section.Go
  • ROM Specifications section: Added section.Go
  • Reference Summary Table: Replaced CONFIG8 bitfield name with ANAREFSEL. Go
  • Analog-to-Digital Converter (ADC) section: Updated bulletpoints under "Each ADC has the following features". Go
  • Changed ADCCLK conversion cycles from 11 ADCCLKs to 12 ADCCLKsGo
  • Changed typical VREFHI input current from 40uA to 200uA for a 2.5V referenceGo
  • Changed typical VREFHI input current from 40uA to 130uA for a 1.65V referenceGo
  • Changed typical gain error (with external reference) from +/-3 LSB to min of -5 LSBGo
  • Changed typical gain error (with external reference) from +/-3 LSB to max of 5 LSBGo
  • Changed typical offset error from +/-2 LSB to min of -5 LSBGo
  • Changed typical offset error from +/-2 LSB to max of 5 LSBGo
  • Changed typical DNL error from -0.999 to 1 LSB to min of >-1 LSBGo
  • Changed typical DNL error from -0.999 to 1 LSB to max of 1 LSBGo
  • Changed typical INL error to min and maxGo
  • Changed typical THD from -80dB to -77dBGo
  • ADC Performance Per Pin section: Added section.Go
  • Per-Channel Parasitic Capacitance for 48-Pin PT LQFP table: Updated table.Go
  • Per-Channel Parasitic Capacitance for 32-Pin RHB VQFN table: Updated table.Go
  • Per-Channel Parasitic Capacitance for 32-Pin VFC LQFP table: Updated table.Go
  • Changed min 1x hysteresis from 2mV to 1mVGo
  • Changed min 2x hysteresis from 8mV to 7mVGo
  • Changed min 3x hysteresis from 15mV to 14mVGo
  • Changed min 4x hysteresis from 20mV to 19mVGo
  • Changed min 5x hysteresis from 26mV to 25mVGo
  • Changed min 6x hysteresis from 32mV to 31mVGo
  • Changed min 7x hysteresis from 38mV to 37mVGo
  • Changed min static INL from -5 LSB to -7 LSBGo
  • Changed max static INL from 5 LSB to 7 LSBGo
  • Changed load regulation from typical +/- 1 mV/V to min -1mV/VGo
  • Changed load regulation from typical +/- 1 mV/V to max 1mV/VGo
  • Added voltage output slew rate minGo
  • Changed voltage output slew rate typical from 2.5V/us to 4.5V/usGo
  • Added voltage output slew rate maxGo
  • Changed load transient settling time max from 700ns to 750nsGo
  • Added min offset errorGo
  • Removed typical offset errorGo
  • Added max offset errorGo
  • Added min DNL Go
  • Removed typical DNLGo
  • Added max DNL Go
  • Added min INL Go
  • Removed typical INLGo
  • Added max INL Go
  • Changed min ADC S+H settling time for all gainsGo
  • Changed typical Ria for 2/-1 gain from 14kOhms to 16kOhmsGo
  • Changed typical Ria for 4/-3 gain from 7kOhms to 8kOhmsGo
  • Changed typical Rib for 2/-1 gain from 14kOhms to 16kOhmsGo
  • Changed typical Rib for 4/-3 gain from 21kOhms to 24kOhmsGo
  • Changed min and max gain errors for gains 2,-1 to 32,-31 Go
  • eQEP Block Diagram: Updated diagram. Go
  • Flash Memory Map table: Deleted F2800135V from PART NUMBER column.Go
  • Direct Memory Access (DMA) section: Added note about DMA accessing EALLOW protected peripheral registers.Go
  • Direct Memory Access (DMA): Updated diagram and "DMA features include" list to add access to PGA and CMPSS peripheral registers. Added software trigger from C28x as a trigger source in block diagram.Go
  • Tape and Reel section: Added 32VFC and 48PT parts to Tape and Reel tables.Go

Changes from July 27, 2025 to September 8, 2025

  • TAPE AND REEL INFORMATION section: Added XF28E120SBTRHBR.Go