SPRUIT1B May   2020  – November 2020

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Key Features
  3. 2GESI Expansion Board Overview
    1. 2.1 GESI Expansion Board Identification
    2. 2.2 GESI Expansion Board Component Identification
  4. 3GESI Expansion Board - User Setup/Configuration
    1. 3.1 GESI Infotainment Expansion Board With CP Board
      1. 3.1.1 Board Assembly Procedures
    2. 3.2 Power Requirements
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM Configuration DIP Switch
  5. 4GESI Expansion Board Hardware Architecture
    1. 4.1  GESI Expansion Board Hardware Top Level Diagram
    2. 4.2  Expansion Connectors
    3. 4.3  Board ID EEPROM
    4. 4.4  Ethernet Interface
      1. 4.4.1 RGMII Clocking Scheme
      2. 4.4.2 Ethernet Port LED Indication
    5. 4.5  PROFI BUS / RS485
    6. 4.6  LIN Interface
    7. 4.7  MCAN
    8. 4.8  MUX Selection
      1. 4.8.1 MUX – PRGx_MDIO/MDC, CPSW9G_MDIO/MDC
      2. 4.8.2 MUX – PRG1_RGMII1/PRG1_PWM
      3. 4.8.3 MUX – PRG1_PWM/MCAN
      4. 4.8.4 MUX_MC/BP_SEL
    9. 4.9  GESI LaunchPad-Booster Pack Interface
    10. 4.10 Motor Control Interface
    11. 4.11 USS/IMU Header
    12. 4.12 Test Header
  6.   A Interface Mapping
  7.   B GESI Board GPIO Mapping
  8.   C I2C Address Mapping
  9.   D Revision History

A Interface Mapping

J721E EVM & J7VCL EVM Interface Mapping on GESI Expansion is provided in Table A-1.

Table A-1 Interface Mapping (1)
GESI Peripheral GESI Interface J721E Connectivity J7200 Connectivity
RGMII Port 1
(U37, J21 Bottom)		 RGMII Port
(Net name PRG0_RGMII1_*)		 RGMII3 / PRG0_RMGII1 RGMII2
MDIO
(Net name PRG0_M*)		 (see mux selection)
MDIO0 or PRG0_MDIO		 MDIO0
RGMII Port 2
(U5, J21 Top)		 RGMII Port
(Net name PRG0_RGMII2_*)		 RGMII4 /PRG0_RGMII2
 <not supported>
MDIO
(Net name PRG0_M*)		 (see mux selection)
MDIO0 or PRG0_MDIO		 <not supported>
RGMII Port 3
(U30, J20 Bottom)		 RGMII Port
(Net name PRG1_RGMII1_*)		 RGMII1 / PRG1_RMGII1 <not supported>
MDIO
(Net name PRG1_M*)		 (see mux selection)
MDIO0 or PRG1_MDIO		 <not supported>
RGMII Port 4
(U3, J20 Top)		 RGMII Port
(Net name PRG1_RGMII2_*)		 RGMII8 /PRG1_RGMII2 <not supported>
MDIO
(Net name PRG1_M*)		 (see mux selection)
MDIO0 or PRG1_MDIO		 <not supported>
RMII Port
(U40, J23)		 RMII (Net name RMII8_*) RMII8 <not supported>
MDIO (Net name MDIO0_M*) MDIO0 <not supported>
CAN Port 1(U15, J14) CAN (Net name MCAN4_*) MCAN4 MCAN4
CAN Port 2(U11, J12) CAN (Net name MCAN5_*) MCAN5 MCAN5
CAN Port 3(U9, J10) CAN (Net name MCAN6_*) MCAN6 MCAN6
CAN Port 4 (U8, J8) CAN (Net name MCAN7_*) MCAN7 MCAN7
CAN Port 5 (U7, J6) CAN (Net name MCAN9_*) MCAN9 MCAN8
CAN Port 6 (U6, J3) CAN (Net name MCAN11_*) MCAN11 MCAN10
LIN Port 1 (U45, J25) UART (Net name LIN1_UART_*) UART8 UART5
LIN Port 2 (U45, J25) UART (Net name LIN2_UART_*) <not supported> UART6
LIN Port 3 (U46, J26) UART (Net name LIN3_UART_*) <not supported> UART9
LIN Port 4 (U46, J26) UART (Net name LIN4_UART_*) <not supported> UART3
LIN Port 5 (U47, J27) UART (Net name LIN5_UART_*) <not supported> UART7
LIN Port 6 (U47, J27) UART (Net name LIN6_UART_*) <not supported> UART1
Config EEPROM(U36) I2C0 (Net name WKUP_I2C0_*) WKUP_I2C0 WKUP_I2C0
ProfiBus(U26, J18) UART
(Net Name MAIN_UART4_*)		 (see mux selection)
UART4 Or PRG1_UART0		 UART3
USS/IMU Header (J19) UART4 (Net name UART3_*) UART3 <not supported>
I2C5 (Net name I2C5_*) (see mux selection) I2C5 <not supported>
BoosterPack Header (J5, J16) UART3 (Net name UART3_*) UART3 <not supported>
SPI3 (Net name SPI3_*) SPI3 <not supported>
Test Connector (J22) UART4(Net Name MAIN_UART4_*) (see mux selection)
UART4 Or PRG1_UART0		 <not supported>
Motor Control Header (J24) I2C5(Net name I2C5_*) (see mux selection) I2C5 <not supported>
SPI3(Net name SPI3_*) SPI3 <not supported>
SPI6(Net name SPI6_*) SPI6 <not supported>
(1) Header and expansion interfaces can support a variety of modes and signals for testing and interfacing to external components. All supported modes are not documented in Table B-1. To determine the complete list of supported signals/interfaces, see device DM and EVM schematics.