SPRUIT1B May   2020  – November 2020

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Key Features
  3. 2GESI Expansion Board Overview
    1. 2.1 GESI Expansion Board Identification
    2. 2.2 GESI Expansion Board Component Identification
  4. 3GESI Expansion Board - User Setup/Configuration
    1. 3.1 GESI Infotainment Expansion Board With CP Board
      1. 3.1.1 Board Assembly Procedures
    2. 3.2 Power Requirements
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM Configuration DIP Switch
  5. 4GESI Expansion Board Hardware Architecture
    1. 4.1  GESI Expansion Board Hardware Top Level Diagram
    2. 4.2  Expansion Connectors
    3. 4.3  Board ID EEPROM
    4. 4.4  Ethernet Interface
      1. 4.4.1 RGMII Clocking Scheme
      2. 4.4.2 Ethernet Port LED Indication
    5. 4.5  PROFI BUS / RS485
    6. 4.6  LIN Interface
    7. 4.7  MCAN
    8. 4.8  MUX Selection
      1. 4.8.1 MUX – PRGx_MDIO/MDC, CPSW9G_MDIO/MDC
      2. 4.8.2 MUX – PRG1_RGMII1/PRG1_PWM
      3. 4.8.3 MUX – PRG1_PWM/MCAN
      4. 4.8.4 MUX_MC/BP_SEL
    9. 4.9  GESI LaunchPad-Booster Pack Interface
    10. 4.10 Motor Control Interface
    11. 4.11 USS/IMU Header
    12. 4.12 Test Header
  6.   A Interface Mapping
  7.   B GESI Board GPIO Mapping
  8.   C I2C Address Mapping
  9.   D Revision History

B GESI Board GPIO Mapping

GESI GPIO mapping is shown in Table B-1.

Table B-1 GPIO Mapping (1)
GESI Peripheral Peripheral I/O Direction (for SoC) Default Active State J721E Connectivity J7VCL Connectivity
RGMII Port 1, Port2 Interrupt Input PU (2) Active Low GPIO1_23 GPIO0_27
Reset Output PU Active Low GPIO0_61 GPIO0_28
RGMII Port 1, Port2 Interrupt Input PU Active Low GPIO1_24 <not supported>
Reset Output PU Active Low GPIO0_62 Pulled down
RMII Port Interrupt Input PU Active Low GPIO0_104 N/A
Reset Output PU Active Low GPIO0_96 N/A
CAN Bus (All Ports) Standby Output PD Active Low GPIO0_60 IO Expander P7,(I2C0: 0X21 on SOM)
LIN Bus (All Ports) Enable Output PD Active High GPIO0_68 IO Expander P6,(I2C0: 0X21 on SOM)
IMU Sensor Header IMU_GPIO0 I/O NA NA GPIO0_105 N/A
IMU_GPIO1 I/O NA NA GPIO0_48 N/A
Boosterpack Header BP_GPIO1 I/O NA NA GPIO1_0 N/A
BP_GPIO2 I/O NA NA GPIO0_127 N/A
BP_GPIO3 I/O NA NA GPIO0_123 N/A
BP_GPIO4 I/O NA NA GPIO0_124 N/A
MCAN/PWM Mux Select Output PD ‘0’ – MCAN
‘1’ - PWM		 I2C0 (0x20), P14 I2C0 (0x20), P14
MDIO PRG0 Mux Select Output PU ‘0’ – PRG0_MDIO
‘1’ – MDIO, I2C5		 I2C0 (0x20), P15 I2C0 (0x20), P15
MDIO PRG1 Mux Select Output PU ‘0’ – PRG1_MDIO
‘1’ – MDIO, UART3		 I2C0 (0x20), P16 I2C0 (0x20), P16
(1) Header and expansion interfaces can support a variety of modes and signals for testing and interfacing to external components. All supported GPIO are not documented in Table B-1. To determine the complete list of supported signals/GPIO, see device-specific DM and EVM schematics.
(2) ‘PU’ refers to default state of Pull-up. ‘PD’ refers to default state of Pull-down.