SPRUJA1A October   2023  – December 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Power Supply
      3. 2.2.3 Memory
      4. 2.2.4 JTAG/Emulator
      5. 2.2.5 Support Interfaces and Peripherals
      6. 2.2.6 Expansion Connectors/Headers
    3. 2.3  Power
      1. 2.3.1 Power Requirements
      2. 2.3.2 Power Input
      3. 2.3.3 Power Supply
      4. 2.3.4 Power Sequencing
      5. 2.3.5 AM62x SIP SoC Power
      6. 2.3.6 Current Monitoring
    4. 2.4  Power ON/OFF Procedure
      1. 2.4.1 Power ON Procedure
      2. 2.4.2 Power OFF Procedure
      3. 2.4.3 Power Test Points
    5. 2.5  Interface Mapping
    6. 2.6  Clocking
      1. 2.6.1 Peripheral Ref Clock
    7. 2.7  Reset
    8. 2.8  CSI Interface
    9. 2.9  Audio Codec Interface
    10. 2.10 HDMI Display Interface
    11. 2.11 JTAG Interface
    12. 2.12 Test Automation Header
    13. 2.13 UART Interface
    14. 2.14 USB Interface
      1. 2.14.1 USB 2.0 Type A Interface
      2. 2.14.2 USB 2.0 Type C Interface
    15. 2.15 Memory Interfaces
      1. 2.15.1 OSPI Interface
      2. 2.15.2 MMC Interfaces
        1. 2.15.2.1 MMC0 - eMMC Interface
        2. 2.15.2.2 MMC1 - Micro SD Interface
        3. 2.15.2.3 MMC2 - M.2 Key E Interface
      3. 2.15.3 Board ID EEPROM
    16. 2.16 Ethernet Interface
      1. 2.16.1 CPSW Ethernet PHY 1 Default Configuration
      2. 2.16.2 CPSW Ethernet PHY 2 Default Configuration
    17. 2.17 GPIO Port Expander
    18. 2.18 GPIO Mapping
    19. 2.19 OLDI Display Interface
    20. 2.20 EVM User Setup/Configuration
      1. 2.20.1 EVM DIP Switches
      2. 2.20.2 Boot Modes
      3. 2.20.3 User Test LEDs
    21. 2.21 Expansion Headers
      1. 2.21.1 PRU Connector
      2. 2.21.2 User Expansion Connector
      3. 2.21.3 MCU Connector
    22. 2.22 Interrupt
    23. 2.23 I2C Address Mapping
  8. 3Hardware Design Files
  9. 4Compliance Information
    1. 4.1 Compliance and Certifications
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
      1. 5.1.1 Issue 1 - OLDI Display Touch Broken
    2. 5.2 Trademarks
    3.     75
  11. 6Revision History

2.20.2 Boot Modes

The boot mode for the AM62x SIP SK EVM board is defined by two banks of switches SW1 and SW2 or by the I2C buffer connected to the Test automation connector. This allows for AM62x SIP SoC Boot mode control by either the user (DIP Switch Control) or by the Test Automation connector.

All the bits of switch (SW1 and SW2) have weak pull-down resistor and a strong pull up resistor as shown in below picture. Note that OFF setting provides a low logic level (‘0’) and an ON setting provides a high logic level (‘1’).

SK-AM62-SIP Boot Mode Switch Configuration for SD Boot Figure 2-27 Boot Mode Switch Configuration for SD Boot

The boot mode pins of the SoC have associated alternate functions during normal operation. Hence isolation is provided using Buffer IC’s to cater for alternate pin functionality. The output of the buffer is connected to the boot mode pins on the AM62x SIP and the output is enabled when the boot mode is needed during a reset cycle.

The input to the buffer is connected to the DIP switch circuit and to the output of an I2C buffer set by the test automation circuit. If the test automation circuit is going to control the bootmode, then all the switches are manually set to the OFF position. The boot mode buffer is powered by an always ON power supply to make sure that the boot mode remains present even if the SoC power is cycled.

Switch SW1 and SW2 bits [15:0] are used to set the SoC Boot mode.

The switch map to the boot mode functions is provided in the tables below.

Table 2-15 Boot Mode Pin Mapping
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Backup boot mode configuration Backup boot mode Primary boot mode configuration Primary boot mode PLLConfiguration

The table below gives details of PLL reference clock selection.

Note: BOOT-MODE[0:2] – Denote system clock frequency for PLL configuration. By default, this bits are set for 25MHz.
Table 2-16 PLL Reference Clock Selection BOOTMODE[2:0]
Bit 2 Bit 1 Bit 0 PLL REF CLK (MHz)
OFF OFF OFF RSVD
OFF OFF ON RSVD
OFF ON OFF 24
OFF ON ON 25
ON OFF OFF 26
ON OFF ON RSVD
ON ON OFF RSVD
ON ON ON RSVD

The table below provides primary boot device selection details.

Note: BOOT-MODE[3:6] – This provides primary boot mode configuration to select the requested boot mode after POR, that is, the peripheral/memory to boot from.
Table 2-17 Boot Device Selection BOOTMODE[6:3]
Bit 6 Bit 5 Bit 4 Bit 3 Primary Boot Device Selected
OFF OFF OFF OFF Serial NAND
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF Ethernet RGMII1
OFF ON OFF ON Ethernet RMII1
OFF ON ON OFF I2C
OFF ON ON ON UART
ON OFF OFF OFF MMC/SD card
ON OFF OFF ON eMMC
ON OFF ON OFF USB0
ON OFF ON ON GPMC NAND
ON ON OFF OFF GPMC NOR
ON ON OFF ON Rsvd
ON ON ON OFF xSPI
ON ON ON ON Noboot/Dev Boot

The table below provides backup boot mode selection details.

Note: BOOT-MODE[10:12] – Select the backup boot mode, that is, the peripheral/memory to boot from, if primary boot device failed.
Table 2-18 Backup Boot Mode Selection BOOTMODE[12:10]
Bit 12 Bit 11 Bit 10 Backup Boot Device Selected
OFF OFF OFF None (no backup mode)
OFF OFF ON USB
OFF ON OFF Reserved
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C

The table below gives primary boot media configuration details.

Note: BOOT-MODE[9:7] – These pins provide optional settings and are used in conjunction with the primary boot device selected.
Table 2-19 Primary Boot Media Configuration BOOTMODE[9:7]
Bit 9 Bit 8 Bit 7 Boot Device
Reserved Read Mode 2 Read Mode 1 Serial NAND
Speed Iclk Csel OSPI
Reserved Iclk Csel QSPI
Reserved Mode Csel SPI
Clkout Delay Link Stat Ethernet RGMII
Clkout Clksrc Reserved Ethernet RMII
BusReset Reserved Addr I2C
Reserved Reserved UART
Port Reserved Fs/raw MMC/ SD card
Reserved Voltage eMMC
Reserved Mode Lane Swap USB0
Reserved GPMC NAND
Reserved GPMC NOR
Reserved Reserved
SFDP Read Cmd Mode xSPI
Reserved No/Dev Noboot/Dev Boot
Table 2-20 Serial NAND Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW2.1] Read Mode 2 0 Reserved (Read mode is taken from Read Mode 1
1

SPI/ 1-1-1 mode (Read mode is taken from Read

Mode 2 and Read Mode 1 is ignored)
7 [SW1.8] Read Mode 1 0 OSPI/ 1-1-8 Mode (valid only when Read Mode 2 is 0)
1 OSPI/ 1-1-4 Mode (valid only when Read Mode 2 is 0)
Table 2-21 OSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW2.1] Iclk 0 Iclock source external
1 Iclock source internal (pad loopback)
7 [SW1.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-22 QSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW2.1] Iclk 0 Iclock source external
1 Iclock source internal (pad loopback)
7 [SW1.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-23 SPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW2.1] Mode 0 SPI Mode 0
1 SPI Mode 3
7 [SW1.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-24 Ethernet RGMII Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW2.2] Clkout 0 25MHz clock not generated on CLKOUT0
1 25MHz clock generated on CLKOUT0

8 [SW2.1]

Delay 0 Must be set to 0 for RGMII with internal Tx delay
1 Reserved
7 [SW1.8] Link info 0 MDIO PHY scan used for link parameters
1 Link parameters programmed by the ROM
Table 2-25 Ethernet RMII Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW2.2] Clkout 0 50MHz clock not generated on CLKOUT0
1 50MHz clock generated on CLKOUT0

8 [SW2.1]

Clk src 0 External clock source for RMII1_REF_CLK
1 Internal clock source for RMII1_REF_CLK
7 [SW1.8] RMII 0 This bit must be set to 0
1 Reserved
Table 2-26 Ethernet RMII Clocking
BOOTMODE Pin 9 (Clk out) BOOTMODE Pin 8 (Clk src) Description
0 0

50MHz external source to RMII_REF_CLK and to external Ethernet

PHY input clock (CLKOUT0 is unused) These are the recommended

settings
0 1 Not a valid configuration
1 0

CLKOUT0 is configured to 50MHz and connect to both

RMII1_REF_CLK and to external Ethernet PHY input clock
1 1 Not a valid configuration
Table 2-27 Ethernet Backup Boot Configuration Field
BOOTMODE Pins Field Value Description
13 [SW2.2] Interface 0 RGMII with internal TX delay
1 RMII with external clock source
Table 2-28 I2C Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW2.2] Bus reset 0 Hung bus reset attempt after 1ms
1 No hung bus reset attempted
7 [SW1.8] Address 0 EEPROM's address is 0x50
1 EEPROM's address is 0x51
Table 2-29 SD Card Boot Configuration Fields
BOOTMODE Pins Field Value Description

9 [SW2.2]

13(1) [SW2.2]

 Port 0 Reserved
1 MMC Port 1 (4 bit width). This bit must be set to 1
7 [SW1.8] FS/Raw 0 Filesystem mode
1 Raw Mode
(1) When MMCSD is the backup mode
Table 2-30 eMMC Boot Configuration Fields
BOOTMODE Pins Field Value Description

9 [SW2.2]

13(1) [SW2.2]

 Port 0 MMCSD Port 0 (8 bit width). This bit must be set to 0
1 Reserved
7 [SW1.8] FS/Raw 0 Filesystem mode
1 Raw Mode
(1) When MMCSD is the backup mode
Table 2-31 USB Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW2.2] Core Voltage 0 0.85V core voltage
1 0.75V core voltage

8 [SW2.1]

13(1) [SW2.2]

 Mode 0 DFU (USB device firmware upgrade)
1 Host (MSC boot)
7 [SW1.8] Lane Swap 0 D+/D- lines are not swapped
1 D+/D- lines are swapped
(1) When USB is the backup mode.
Table 2-32 xSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW2.2] SFDP 0 SFDP disabled
1 SFDP enabled

8 [SW2.1]

Read cmd 0 0x0B Read Command
1 0xEE Read Command
7 [SW1.8] Mode 0 1S-1S-1S mode @ 50MHz
1 8D-8D-8D mode @ 25MHz

The table below provides backup boot media configuration options.

Note:
  • BOOT-MODE[13] – These pins provide optional settings and are used in conjunction with the backup boot device devices. Switch SW2.6 when ON sets 1 and sets 0 if OFF, see the device-specific TRM.
  • BOOT-MODE[14:15] – Reserved.
Table 2-33 Backup Boot Media Configuration BOOTMODE[13]
Bit 13 Boot Device
Reserved None
Mode USB
Reserved Reserved
Reserved UART
IF Ethernet
Port MMC/SD
Reserved SPI
Reserved I2C