SPRUJA1A October   2023  – December 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Power Supply
      3. 2.2.3 Memory
      4. 2.2.4 JTAG/Emulator
      5. 2.2.5 Support Interfaces and Peripherals
      6. 2.2.6 Expansion Connectors/Headers
    3. 2.3  Power
      1. 2.3.1 Power Requirements
      2. 2.3.2 Power Input
      3. 2.3.3 Power Supply
      4. 2.3.4 Power Sequencing
      5. 2.3.5 AM62x SIP SoC Power
      6. 2.3.6 Current Monitoring
    4. 2.4  Power ON/OFF Procedure
      1. 2.4.1 Power ON Procedure
      2. 2.4.2 Power OFF Procedure
      3. 2.4.3 Power Test Points
    5. 2.5  Interface Mapping
    6. 2.6  Clocking
      1. 2.6.1 Peripheral Ref Clock
    7. 2.7  Reset
    8. 2.8  CSI Interface
    9. 2.9  Audio Codec Interface
    10. 2.10 HDMI Display Interface
    11. 2.11 JTAG Interface
    12. 2.12 Test Automation Header
    13. 2.13 UART Interface
    14. 2.14 USB Interface
      1. 2.14.1 USB 2.0 Type A Interface
      2. 2.14.2 USB 2.0 Type C Interface
    15. 2.15 Memory Interfaces
      1. 2.15.1 OSPI Interface
      2. 2.15.2 MMC Interfaces
        1. 2.15.2.1 MMC0 - eMMC Interface
        2. 2.15.2.2 MMC1 - Micro SD Interface
        3. 2.15.2.3 MMC2 - M.2 Key E Interface
      3. 2.15.3 Board ID EEPROM
    16. 2.16 Ethernet Interface
      1. 2.16.1 CPSW Ethernet PHY 1 Default Configuration
      2. 2.16.2 CPSW Ethernet PHY 2 Default Configuration
    17. 2.17 GPIO Port Expander
    18. 2.18 GPIO Mapping
    19. 2.19 OLDI Display Interface
    20. 2.20 EVM User Setup/Configuration
      1. 2.20.1 EVM DIP Switches
      2. 2.20.2 Boot Modes
      3. 2.20.3 User Test LEDs
    21. 2.21 Expansion Headers
      1. 2.21.1 PRU Connector
      2. 2.21.2 User Expansion Connector
      3. 2.21.3 MCU Connector
    22. 2.22 Interrupt
    23. 2.23 I2C Address Mapping
  8. 3Hardware Design Files
  9. 4Compliance Information
    1. 4.1 Compliance and Certifications
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
      1. 5.1.1 Issue 1 - OLDI Display Touch Broken
    2. 5.2 Trademarks
    3.     75
  11. 6Revision History

2.16.1 CPSW Ethernet PHY 1 Default Configuration

The default configuration of the DP83867 is determined using a number of resistor pull-up and pull-down values on specific pins of the PHY. Depending on the values installed, each of the configuration pins can be set to one of four modes by using the pull up and pull down options provided. The AM62x SIP SK EVM uses the 48-pin QFN package which supports the RGMII interface.

The DP83867 PHY uses four level configurations based on resistor strapping which generate four distinct voltages ranges. The resistors are connected to the RX data and control pins which are normally driven by the PHY and are inputs to the processor. The voltage range for each mode is shown below:

Mode1 - 0V to 0.3V

Mode2 – 0.462V to 0.6303V

Mode3 – 0.7425V to 0.9372V

Mode4 – 2.2902V to 2.9304V

Footprint for both pull-up and pull-down is provided on all the strapping pins except LED_0. LED_0 is for Mirror Enable, which is set to mode 1 by default, Mode 4 is not applicable and Mode2, Mode3 option is not desired.

CPSW_RGMII1 port of the AM62x SIP SoC is connected to DP83867 whose configuration is as given below:

PHYADDR: 00000

Auto_neg: Enabled

ANGsel 10/100/1000

RGMII Clk skew Tx: 2ns

RGMII Clk skew Rx: 2ns