SPRUJE7A January 2025 – July 2025 F29H850TU , F29H859TU-Q1
SECCFG sectors are a portion of Flash memory designated for storing the SSU user configuration, or User Protection Policy (UPP). Each CPU has an active SECCFG start address, and an alternate (reserve) SECCFG start address. The reserve (alternate) SECCFG sectors' start address can be used when erasing/programming SECCFG sector when using flash API. For SECCFG configuration details, see the F29H85x and F29P58x Real-Time Microcontrollers Technical Reference Manual.
| Bank Mode | CPUxSWAP | Region | CPU1/CPU2 Bank | CPU1 Address | CPU2 Address | CPU3 Bank | CPU3 Address |
|---|---|---|---|---|---|---|---|
| Mode 0 | Active | FLC1.B0/B1 | 0x10D8 1000 | 0x10D8 1800 | FLC2.B0/B1 | 0x10D8 9000 | |
| Alternate | FLC1.B2/B3 | 0x10D8 5000 | 0x10D8 5800 | FLC2.B2/B3 | 0x10D8 D000 | ||
| Mode 1 | SWAP = 0 | Active | FLC1.B0/B1 | 0x10D8 1000 | 0x10D8 1800 | FLC2.B0/B1 | 0x10D8 5000 |
| Alternate | FLC1.B2/B3 | 0x10D9 9000 | 0x10D9 9800 | FLC2.B2/B3 | 0x10D9 D000 | ||
| SWAP = 1 | Active | FLC1.B2/B3 | 0x10D8 1000 | 0x10D8 1800 | FLC2.B2/B3 | 0x10D8 5000 | |
| Alternate | FLC1.B0/B1 | 0x10D9 9000 | 0x10D9 9800 | FLC2.B0/B1 | 0x10D9 D000 | ||
| Mode 2 | Active | FLC1.B0/B1 | 0x10D8 1000 | 0x10D8 1800 | FLC2.B0/B1 | 0x10D9 1000 | |
| Alternate | FLC1.B2/B3 | 0x10D8 5000 | 0x10D8 5800 | FLC2.B2/B3 | 0x10D9 5000 | ||
| Mode 3 | SWAP = 0 | Active | FLC1.B0/B1 | 0x10D8 1000 | 0x10D8 1800 | FLC2.B0/B1 | 0x10D9 1000 |
| Alternate | FLC1.B2/B3 | 0x10D9 9000 | 0x10D9 9800 | FLC2.B2/B3 | 0x10D9 D000 | ||
| SWAP = 1 | Active | FLC1.B2/B3 | 0x10D8 1000 | 0x10D8 1800 | FLC2.B2/B3 | 0x10D9 1000 | |
| Alternate | FLC1.B0/B1 | 0x10D9 9000 | 0x10D9 9800 | FLC2.B0/B1 | 0x10D9 D000 |
Steps for programming SECCFG are as follows: