SPRUJG5 January 2025
The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of operation.
| Functional Pin | Mode on DP83867-EVM-AM | Function |
|---|---|---|
| RX_D0 | EEPROM_A0 | PHY address: 0[EEPROM_A2][EEPROM_A0]. See Section 2.6.1.4 for more information on PHY addressing. |
| RX_D2 | EEPROM_A2 | |
| RX_DV/RX_CTRL | 3 | Auto negotiation enabled |
| LED_1 | 1 | Clock Skew TX[2] = 2 ns Advertise ability of 10/100/1000 Mbps |
| LED_2 | 1 | Clock Skew TX[1] = 2 ns Clock Skew TX[0] = 2 ns |
| GPIO0 | 1 | Clock Skew RX[0] = 2 ns |
| GPIO1 | 1 | Clock Skew RX[2] = 2 ns Clock Skew RX[1] = 2 ns |