SPRUJG5 January   2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1.     Preface: Read This First
      1. 1.1.1 If You Need Assistance
    2. 1.1 Introduction
    3. 1.2 Kit Contents
    4. 1.3 Device Information
  6. 2Hardware
    1. 2.1 Component Identification
    2. 2.2 Power Requirements
      1. 2.2.1 Power Tree
    3. 2.3 Functional Block Diagram
    4. 2.4 Header Information
    5. 2.5 Test Points
    6. 2.6 Interfaces
      1. 2.6.1 Ethernet Interface
        1. 2.6.1.1 Industrial Ethernet PHY
        2. 2.6.1.2 Industrial Ethernet PHY Strapping Resistors
        3. 2.6.1.3 LED Indication in RJ45 Connector
        4. 2.6.1.4 Multi-Connector Addressing
    7. 2.7 Integration Guide
      1. 2.7.1 Board Dimensions
      2. 2.7.2 Installation
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 Trademarks
  9. 5References
    1. 5.1 Reference Documents
  10. 6Revision History

1.3 Device Information

The DP83867 is a fully featured Physical Layer transceiver with integrated PMD sub-layers to support 10BASETe, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83867 is designed for easy implementation of 10/100/1000Mbps Ethernet LANs. It interfaces directly to twisted pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).

The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low jitter, low latency and provides IEEE 1588 Start of Frame Detection for time sensitive protocols.

The DP83867 offers innovative diagnostic features including dynamic link quality monitoring for fault prediction during normal operation. It can support up to 130m cable length.

For additional information, refer to the DP83867IR Data Sheet