SPRUJG5 January   2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1.     Preface: Read This First
      1. 1.1.1 If You Need Assistance
    2. 1.1 Introduction
    3. 1.2 Kit Contents
    4. 1.3 Device Information
  6. 2Hardware
    1. 2.1 Component Identification
    2. 2.2 Power Requirements
      1. 2.2.1 Power Tree
    3. 2.3 Functional Block Diagram
    4. 2.4 Header Information
    5. 2.5 Test Points
    6. 2.6 Interfaces
      1. 2.6.1 Ethernet Interface
        1. 2.6.1.1 Industrial Ethernet PHY
        2. 2.6.1.2 Industrial Ethernet PHY Strapping Resistors
        3. 2.6.1.3 LED Indication in RJ45 Connector
        4. 2.6.1.4 Multi-Connector Addressing
    7. 2.7 Integration Guide
      1. 2.7.1 Board Dimensions
      2. 2.7.2 Installation
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 Trademarks
  9. 5References
    1. 5.1 Reference Documents
  10. 6Revision History

2.6.1.1 Industrial Ethernet PHY

The AMx EVM Industrial Ethernet PHY Add-on Board uses one port of RGMII signals to be connected to a 32-pin Ethernet PHY (DP83867IR). The PHY is configured to advertise 10/100/1000 Mb operation. The Ethernet data signals of the PHY are terminated to an RJ45 Connector. LEDs are used to indicate link status and activity.

Figure 2-5 Industrial Ethernet PHY AUDIO-AM275-EVM AUDIO-AM62D-EVM

The Ethernet PHY requires three power sources, VDDIO (3.3V or 1.8V), VDDA2P5 (2.5V), and VDD1P0 (VDD_1V0) which are supplied through the DF40GB connector (J1).

On some EVMs, the RGMII port of the CPSW signals are internally muxed on the same balls of the MCU as the PRU-ICSS Ethernet signals. To use RGMII, the balls must be set to the appropriate mux mode for RGMII.

The MDIO and Interrupt signals from the main EVM SoC to the PHY require 2.2KΩ pull up resistors to the I/O supply voltage for proper operation. These resistors are not assembled by default on the DP83867-EVM-AM, but there are footprints if the main EVM does not have these signals pulled up. The interrupt signal is driven by a GPIO signal that is mapped from the main EVM SoC.

The reset signal for the Ethernet PHY is most often driven by a 2-input AND gate. The AND gate's inputs are a GPIO signal that is generated by the main SoC EVM and a reset status signal on the main EVM.