SPRUJG7 May   2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
      1. 1.1.1 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 System Components
      1. 2.1.1 System Components Top
      2. 2.1.2 System Components Bottom
    2. 2.2 Power Requirements
    3. 2.3 Setup
    4. 2.4 Header Information
      1. 2.4.1 Connector Pinout
      2. 2.4.2 Debug Connector Pinouts
    5. 2.5 Interfaces
    6. 2.6 Switch Information
    7. 2.7 Indicator LED
    8. 2.8 Test Points
  7. 3Software
  8. 4Hardware Design Files
  9. 5References
  10. 6Trademarks
  11. 7Revision History

2.1 System Components

The highlight of the TAS67CD-AEC is the two TAS6754-Q1 (TAS67x), 4-channel, Class-D audio amplifier devices (U5, U7) and the supporting components for these devices. The AEC connector (J1) provides I/O power (IOVDD), resets, I2C control, and MCASP TDM data stream from an attached host processor. A low-current, 5V accessory power rail (VSYS5V) is also provided from the AEC for LED and heatsink fans.

TAS67CD-AEC TAS67CD-AEC System Block Diagram Figure 2-1 TAS67CD-AEC System Block Diagram

TAS67x high-current amplifier power (PVDD) and accessory battery power (VBAT) are provided through a set of banana plugs which feed into an LM74502 reverse-polarity, over-voltage, and over-current protection circuit.

MCASP TDM audio data is provided from the MCASPX port of the AEC connector. The MCASP TDM signals are buffered through a set of LMK1C1102 1:2 buffers with each output going to one of the TAS67x amplifiers. MCASP Frame Sync (FSYNC) is buffered through an LMK1C1104 1:4 buffer, with two of the outputs routed to the onboard TAS67x amplifiers and two outputs routed back to the AEC to provide frame-sync synchronization feedback for the host processor through the AEC ECAP pins.

A manual switch (SW1) is provided for selecting between PORZ and RESETSTATZ AEC reset paths. Each TAS67x also has switches (SW2, SW4) for toggling the GPIO0/MUTE# optional input to the TAS67x devices.

Breakout/debug headers (J2, J3) provide an easy to probe location for all of the AEC signals used on the design and most of the unused AEC signals as well.