SPRZ444C February   2018  – November 2026 DRA780 , DRA781 , DRA782 , DRA783 , DRA786 , DRA787

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     i202
    2.     i694
    3.     i727
    4.     i729
    5.     i767
    6.     i813
    7.     i814
    8.     i826
    9.     i829
    10.     i872
    11.     i874
    12.     i879
    13.     i883
    14.     i889
    15.     i893
    16.     i894
    17.     i898
    18.     i899
    19.     i914
    20.     i916
    21.     i930
    22.     i936
    23.     i938
    24.     i939
    25.     i940
  4. 3Silicon Limitations
    1.     i833
    2.     i873
    3.     i876
    4.     i877
  5. 4Silicon Cautions
    1.     i781
    2.     i827
    3.     i828
    4.     i836
    5.     i839
    6.     i864
    7.     i886
    8.     i912
  6. 5Revision History

i936

DSS LCD/DPI Out Field Reversal in Interlaced RGB Mode

CRITICALITY

High

DESCRIPTION

Interlaced RGB mode if set on DSS DPI outputs (VOUT1/2/3) can result in display artifacts due to field reversal. DSS does not support an interlaced compliant VSYNC signal on the DPI output. If the external device/monitor hooked to the DSS in this mode requires an interlaced compliant VSYNC signal then it will have this issue randomly. If the external monitor is able to lock the polarity correctly then the display will be correct otherwise the display will generate field reversed view.

WORKAROUND

Use Interlaced YUV mode with embedded sync (BT.656, BT.1120) if possible.

REVISIONS IMPACTED

SR 2.0A, 2.0

TDA3x: 2.0A, 2.0, 1.0A, 1.0

DRA78x: 2.0A, 2.0

DM50x: 2.0