SoC processor w/ 500 MHz C66x DSP and 2 dual Arm Cortex-M4 for audio amplifier
Product details
Parameters
Features
- Architecture designed for infotainment applications
- Up to 2 C66x floating-point VLIW DSP
- Fully object-code compatible with C67x and C64x+
- Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
- Up to 512kB of on-chip L3 RAM
- Level 3 (L3) and Level 4 (L4) interconnects
- Memory Interface (EMIF) module
- Supports DDR3/DDR3L up to DDR-1066
- Supports DDR2 up to DDR-800
- Up to 2GB supported
- Dual Arm® Cortex®-M4 (IPU)
- Vision
accelerationPac
- Embedded Vision Engine (EVE)
- Display
subsystem
- Display controller with DMA engine
- CVIDEO / SD-DAC TV analog composite output
- On-chip temperature sensor that is capable of generating temperature alerts
- General-Purpose Memory Controller (GPMC)
- Enhanced Direct Memory Access (EDMA) controller
- 3-port (2 external) Gigabit Ethernet (GMAC) switch
- Controller Area Network (DCAN) module
- CAN 2.0B protocol
- Modular Controller Area Network (MCAN)
module
- CAN 2.0B protocol
- Eight 32-bit general-purpose timers
- Three configurable UART modules
- Four Multichannel Serial Peripheral Interfaces (McSPI)
- Quad SPI interface
- Two Inter-Integrated Circuit (I2C™) ports
- Three Multichannel Audio Serial Port (McASP) modules
- Secure Digital Input Output Interface (SDIO)
- Up to 126 General-Purpose I/O (GPIO) pins
- Power, reset, and clock management
- On-chip debug with CTools technology
- Automotive AEC-Q100 qualified
- 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
- Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
- 8-channel 10-bit ADC
- PWMSS
- Video
and image processing support
- Full-HD video (1920 × 1080p, 60 fps)
- Video input and video output
- GPIOs when not used for video
- Video Input Port (VIP)
module
- Support for up to 4 multiplexed input ports
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Description
The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.
Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.
The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.
The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.
The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.
Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.
The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.
The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The Jacinto™ DRA78x evaluation module (EVM) is an evaluation platform designed to speed up development efforts and reduce time-to-market for Radio Signal Processor (RSP) applications. The EVM is based on the Jacinto DRA78x SoC, which incorporates a heterogeneous, scalable architecture (...)
Features
- Hardware
- DRA78x Processor
- 512MB DDR3L
- LP8733/LP8732 Power Management ICs
- Quad-SPI: 1Gbit
- NOR: 512Mbit
- Software
- Linux
- Android
- StarterWare
- Connectivity
- Gigabit Ethernet
- Micro SD Card
- HDMI
- FPD-Link III, Serializer and De-serializer
- CAN Interface, 2-wire PHY
- CAN-FD Interface, 2-wire PHY
Software development
Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)
Features
- Open Linux support
- Linux kernel and Bootloaders
- File system
- Qt/Webkit application framework
- 3D graphics support
- 2D graphics support
- Integrated WLAN and Bluetooth® support
- GUI-based application launcher
- Example applications, including:
- ARM benchmarks: Dhrystone, Linpack (...)
Features
The XDS110 is the latest entry level debug probe (emulators) for TI embedded processors. Designed to be a complete solution that delivers JTAG and SWD connectivity at a low cost, the XDS110 is the debug probe of choice for entry-level debugging of TI microcontrollers, processors and SimpleLink (...)
Design tools & simulation
- Visualize the device clock tree
- Interact with clock tree elements (...)
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| FCBGA (ABF) | 367 | View options |
Ordering & quality
Support & training
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Training series
View all TI training and videosVideos
Integrated Digital Cockpit with Jacinto™ DRA76x
Digital cluster and head unit leverage the performance and integration of one Jacinto DRA76x SoC to power a multi-OS integrated cockpit with 3D surround view.
