DRA783

ACTIVE

SoC processor w/ 2x 750 MHz C66x DSP and 2 dual Arm Cortex-M4 for audio amplifier

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Product details

Parameters

DSP 2 C66x DSP MHz (Max) 750 DRAM DDR2-800, DDR3-1066, DDR3L-1066 Co-processor(s) 2 Dual ARM Cortex-M4 Hardware accelerators 1 Audio Tracking Logic EMIF 1 32-bit Other on-chip memory 512 KB Ethernet MAC 1000, 2-port 1Gb switch Parallel video input ports 4 Display type 1 LCD OUT, 1 SD-DAC Serial I/O CAN, CAN-FD, I2C, QSPI, SPI, UART Storage interface 1x SDIO 4b PCIe 2 PCIe Gen2 McASP 3 TI functional safety category Functional Safety-Compliant open-in-new Find other DRAx digital cockpit SoCs

Features

  • Architecture designed for infotainment applications
  • Up to 2 C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512kB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Memory Interface (EMIF) module
    • Supports DDR3/DDR3L up to DDR-1066
    • Supports DDR2 up to DDR-800
    • Up to 2GB supported
  • Dual Arm® Cortex®-M4 (IPU)
  • Vision accelerationPac
    • Embedded Vision Engine (EVE)
  • Display subsystem
    • Display controller with DMA engine
    • CVIDEO / SD-DAC TV analog composite output
  • On-chip temperature sensor that is capable of generating temperature alerts
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 3-port (2 external) Gigabit Ethernet (GMAC) switch
  • Controller Area Network (DCAN) module
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol
  • Eight 32-bit general-purpose timers
  • Three configurable UART modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Two Inter-Integrated Circuit (I2C™) ports
  • Three Multichannel Audio Serial Port (McASP) modules
  • Secure Digital Input Output Interface (SDIO)
  • Up to 126 General-Purpose I/O (GPIO) pins
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
  • Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
  • 8-channel 10-bit ADC
  • PWMSS
  • Video and image processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Video input and video output
    • GPIOs when not used for video
  • Video Input Port (VIP) module
    • Support for up to 4 multiplexed input ports

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Description

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet DRA78x Infotainment Applications Processor datasheet (Rev. H) Feb. 04, 2020
* Errata DRA78x Silicon Errata (Rev. B) Oct. 01, 2019
Application notes IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC Aug. 24, 2020
Application notes AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) Jan. 06, 2020
User guides DRA78x Technical Reference Manual (Rev. D) Jul. 30, 2019
Application notes Integrating New Cameras With Video Input Port on DRA7xx SoCs Jun. 11, 2019
Application notes Achieving Early CAN Response on DRA7xx Devices Nov. 28, 2018
Application notes DRA74x_75x/DRA72x Performance (Rev. A) Oct. 31, 2018
Application notes Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices Sep. 14, 2018
Application notes The Implementation of YUV422 Output for SRV Aug. 02, 2018
Application notes MMC DLL Tuning (Rev. B) Jul. 31, 2018
Application notes Integrating AUTOSAR on TI SoC: Fundamentals Jun. 18, 2018
Application notes ECC/EDC on TDAxx (Rev. B) Jun. 13, 2018
Application notes Tools and Techniques to Root Case Failures in Video Capture Subsystem Jun. 12, 2018
Application notes Sharing VPE Between VISIONSDK and PSDKLA May 04, 2018
Technical articles Smart sensors are going to change how you drive (because eventually, you won’t) Apr. 25, 2018
Application notes Android Boot Optimization on DRA7xx Devices (Rev. A) Feb. 13, 2018
Technical articles AI in Automotive: Practical deep learning Feb. 08, 2018
Technical articles How to maintain automotive front camera thermal performance on a hot summer day Feb. 02, 2018
Technical articles Development platforms pave the way to production systems for ADAS Jan. 19, 2018
Application notes Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) Nov. 30, 2017
Application notes Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) Nov. 27, 2017
Application notes Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) Nov. 07, 2017
Application notes A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) Nov. 03, 2017
Application notes Optimization of GPU-Based Surround View on TI’s TDA2x SoC Sep. 12, 2017
Application notes Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices Aug. 14, 2017
Application notes Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices Jul. 12, 2017
User guides DRA78x_15X15 EVM CPU Board User's Guide May 22, 2017
User guides TDA3x_15X15 EVM CPU Board Users Guide May 10, 2017
Application notes Linux Boot Time Optimizations on DRA7xx Devices Mar. 31, 2017
Application notes Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) Feb. 17, 2017
Application notes Early Splash Screen on DRA7x Devices Jan. 31, 2017
Application notes Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) Dec. 15, 2016
Application notes Gstreamer Migration Guidelines Apr. 26, 2016
Application notes Flashing Binaries to DRA7xx Factory Boards Using DFU Apr. 14, 2016
Application notes Tools and Techniques for Audio Debugging Apr. 13, 2016
Application notes Debugging Tools and Techniques With IPC3.x Mar. 30, 2016
Application notes Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) Jan. 15, 2016
White papers Informational ADAS as Software Upgrade to Today’s Infotainment Systems Oct. 14, 2014
Application notes Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device Aug. 13, 2014
White papers Today’s high-end infotainment soon becoming mainstream Jun. 02, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
1580.77
Description

The Jacinto™ DRA78x evaluation module (EVM) is an evaluation platform designed to speed up development efforts and reduce time-to-market for Radio Signal Processor (RSP) applications. The EVM is based on the Jacinto DRA78x SoC, which incorporates a heterogeneous, scalable architecture (...)

Features
  • Hardware
    • DRA78x Processor
    • 512MB DDR3L
    • LP8733/LP8732 Power Management ICs
    • Quad-SPI: 1Gbit
    • NOR: 512Mbit
  • Software
    • Linux
    • Android
    • StarterWare
  • Connectivity
    • Gigabit Ethernet
    • Micro SD Card
    • HDMI
    • FPD-Link III, Serializer and De-serializer
    • CAN Interface, 2-wire PHY
    • CAN-FD Interface, 2-wire PHY

Software development

SOFTWARE DEVELOPMENT KITS (SDK) Download
Processor Software Development Kit for DRA7x Jacinto™ Processors – Linux, Android, and RTOS
PROCESSOR-SDK-DRA7X Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Features
Processor SDK Linux Automotive features
  • Open Linux support
  • Linux kernel and Bootloaders
  • File system
  • Qt/Webkit application framework
  • 3D graphics support
  • 2D graphics support
  • Integrated WLAN and Bluetooth® support
  • GUI-based application launcher
  • Example applications, including:
    • ARM benchmarks: Dhrystone, Linpack (...)
DEBUG PROBES Download
XDS110 JTAG Debug Probe
TMDSEMU110-U The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded processors. The XDS110 replaces the XDS100 family while supporting a wider variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes support Core and System Trace in all ARM and (...)
99
Features

The XDS110 is the latest entry level debug probe (emulators) for TI embedded processors. Designed to be a complete solution that delivers JTAG and SWD connectivity at a low cost, the XDS110 is the debug probe of choice for entry-level debugging of TI microcontrollers, processors and SimpleLink (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM703.ZIP (10940 KB) - IBIS Model
SIMULATION MODELS Download
SPRM704.ZIP (1 KB) - Thermal Model
SIMULATION MODELS Download
SPRM713.ZIP (9 KB) - BSDL Model
CALCULATION TOOLS Download
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
FCBGA (ABF) 367 View options

Ordering & quality

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